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參數資料
| 型號： | 873996AYLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 873996 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| 封裝： | 7 X 7 MM, 1 MM HEIGHT, ROHS COMPLIANT, MS-026ABC-HD, TQFP-48 |
| 文件頁數： | 21/21頁 |
| 文件大?。?/td> | 352K |
| 代理商： | 873996AYLF |
IDT / ICS 3.3V LVPECL ZERO DELAY/MULTIPLIER/DIVIDER
9
ICS873996AY REV. A FEBRUARY 19, 2008
ICS873996
DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY/MULTIPLIER/DIVIDER
APPLICATIONS INFORMATION
CLOCK REDUNDANCY AND REFERENCE SELECTION
The ICS873996 accepts two differential input clocks, CLK0/nCLK0
and CLK1/nCLK1, for the purpose of redundancy. Only one of
these clocks can be selected at any given time for use as the
reference. One clock will be defined during the initialization
process as the initial, or primary clock, while the remaining clock
is the redundant or secondary clock. During the initialization
process, input signal SEL_CLK determines which input clock will
be used as the initial clock. When SEL_CLK is driven HIGH, the
initial clock to be used as the reference is CLK1/nCLK1, otherwise
an internal pulldown pulls this input LOW so that the initial clock
input is CLK0/nCLK0. The output signal CLK_INDICATOR
indicates which clock input is being used as the reference (LOW
= CLK0/nCLK0, HIGH = CLK1/nCLK1), and will initially be at the
same level as SEL_CLK.
INITIALIZATION EVENT
An initialization event is required to specify the initial input
clock. In order to run an initialization event, nINIT must transition
from HIGH-to-LOW. Following a HIGH-to-LOW transition of
nINIT, the input clock specified on the SEL_CLK input will
be set as the initial input clock. In addition, both input-bad
flags (INP0BAD and INP1BAD outputs) will be cleared.
FALILURE DETECTION AND ALARM SIGNALING
Within the ICS873996 device, CLK0/nCLK0 and CLK1/nCLK1
are continuously monitored for failures. A failure on either of
these clocks is detected when one of the clock signals is stuck
HIGH or LOW for at least 1 period of the Feedback. Upon
detection of a failure, the corresponding input-bad signal,
INP0BAD or INP1BAD, will be set HIGH. The input clocks are
continuously monitored and the input-bad signals will con-
tinue to reflect the real-time status of each input clock.
MANUAL CLOCK SWITCHING
When input signal MAN_OVERRIDE is driven HIGH, the clock
specified by SEL_CLK will always be used as the
reference, even when a clock failure is detected at the
reference. In order to switch between CLK0/nCLK0 and CLK1/
nCLK1 as the reference clock, the level on SEL_CLK must be
dr i ven to the appropr iate level. When the level on
SEL_CLK is changed, the selection of the new clock will
take place, and CLK_INDICATOR will be updated to indi-
cate which clock is now supplying the reference to the PLL.
DYNAMIC CLOCK SWITCHING
The Dynamic Clock Switching (DCS) process serves as an
automatic safety mechanism to protect the stability of the PLL
when a failure occurs on the reference.
When input signal MAN_OVERRIDE is not driven HIGH, an
internal pulldown pulls it LOW so that DCS is enabled. If DCS
is enabled and a failure occurs on the initial clock, the
ICS873996 device will check the status of the secondary clock.
If the secondary clock is detected as a good input clock, the
ICS873996 will automatically deselect the initial clock as the
reference and multiplex in the secondary clock. When a
successful switch from the initial to secondary clock has
been accomplished, CLK_INDICATOR will be updated to
indicate the new reference. If and when the fault on the initial
clock is corrected, the corresponding input bad flag will be
updated to represent this clock as good again. However, the DCS
will not undergo an unneccessar y clock switch as long
as the secondary clock remains good. If, at a later time, a failure
occurs on the secondary clock, the ICS873996 will then switch to
the initial clock if it is detected as good. See the Dynamic Clock
Switch State Diagram (page 10) and for additional details on the
functionality of the Dynamic Clock Switching circuit.
OUTPUT TRANSITIONING
After a successful manual or DCS initiated clock switch, the
internal PLL of the ICS873996 will begin slewing to phase/
frequency alignment. The PLL will achieve lock to the new
input with minimal phase disturbance at the outputs.
MASTER RESET OPERATION
When the input signal is driven LOW, the internal dividers of
the ICS873996 are reset causing the true outputs, Qx, to go
LOW and the inverted outputs, nQx, to go HIGH. With no signal
driving nMR, an internal pullup pulls nMR HIGH and the output
clocks and internal dividers are enabled.
RECOMMENDED POWER-UP SEQUENCE
1. Before startup, set MAN_OVERRIDE HIGH and set
SEL_CLK to the desired input clock. This will ensure that,
during startup, the PLL will acquire lock using the input clock
specified by SEL_CLK.
2. Once powered-up, and assuming a stable clock free of fail-
ures is present at the clock designated by SEL_CLK, the
PLL will begin to phase/frequency slew as it attempts to
achieve lock with the input reference clock.
3. Drive MAN_OVERRIDE LOW to enable DCS mode.
4. Transition nINIT from HIGH-to-LOW in order to clear both
input-bad flags and to set the initial input clock.
ALTERNATE POWER-UP SEQUENCE
If both input clocks are valid before power up, the part may be
powered-up in DCS mode. However, it cannot be guaranteed
that the PLL will achieve lock with one specific input clock.
1. Before startup, leave MAN_OVERRIDE floating and the
internal pulldown will enable DCS mode.
2. Once powered up, the PLL will begin to phase/frequency
slew as it attempts to achieve lock with one of the input refer-
ence clocks.
3. Transition nINIT from HIGH-to-LOW in order to clear both
input-bad flags and to set the initial input clock.
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相關代理商/技術參數 |
參數描述 |
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| 873996AYLFT | 功能描述:時鐘發(fā)生器及支持產品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 873996AYT | 制造商:Integrated Device Technology Inc 功能描述:Zero Delay PLL Clock Multiplier Single 48-Pin TQFP EP T/R 制造商:Integrated Device Technology Inc 功能描述:873996AYT - Tape and Reel |
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