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參數(shù)資料
| 型號： | 854L4B |
| 英文描述： | Analog Filter |
| 中文描述： | 模擬濾波器 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 660K |
| 代理商： | 854L4B |
8-Bit Programmable Filters
Digital Tuning Characteristics
854 Series
Digital Tuning &
Control Characteristics
25 Locust St. Haverhill, Massachusetts 01830 (800) 252-7074 (978) 374-0761 FAX (978) 521-1839
e-mail: sales@freqdev.com Web Address: http://www.freqdev.com Fax on Demand: 978/521-5178
2
MSB
---
---
---
---
---
---
LSB
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
0
0
0
0
0
0
0
0
f
max
/256
0
0
0
0
0
0
0
1
f
max
/128
0
0
0
0
0
0
1
1
f
max
/64
0
0
0
0
0
1
1
1
f
max
/32
0
0
0
0
1
1
1
1
f
max
/16
0
0
0
1
1
1
1
1
f
max
/8
0
0
1
1
1
1
1
1
f
max
/4
0
1
1
1
1
1
1
1
f
max
/2
1
1
1
1
1
1
1
1
fmax
Bit
Weight
fc
Corner
Frequency
+Vs
OUT
-Vs
D
D
D
D
GND
D
D
D
D
C
P
IN
Bottom View
Os
4
5
3
2
1
0
6
7
Pin-Out Key
IN
OUT Analog Output Signal
GND Power and Signal Return
"P"
Transition Polarity Bit
"C"
Tuning Strobe Bit
+Vs
Supply Voltage, Positive
-Vs
Supply Voltage, Negative
Os
Optional Offset Adjustment
Analog Input Signal
D
7
Tuning Bit 7 (MSB)
D
6
Tuning Bit 6
D
5
Tuning Bit 5
D
4
Tuning Bit 4
D
3
Tuning Bit 3
D
2
Tuning Bit 2
D
1
Tuning Bit 1
D
0
Tuning Bit 0 (LSB)
The digital tuning interface circuits are two 4042 quad CMOS
latches which accept the following CMOS-compatible inputs:
eight tuning bits (D
0
- D
7
), a latch strobe bit (C), and a transition
polarity bit (P).
Filter tuning follows the tuning equation given below:
f
c
= ( f
max
/256 ) [ 1 + D
7
x 2
7
+ D
6
x 2
6
+ D
5
x 2
5
+ D
4
x 2
4
+ D
3
x 2
3
+ D
2
x 2
2
+ D
1
x 2
1
+ D
0
x 2
0
]
where D
1
- D
7
= "0" or "1", and
f
max
= Maximum tuning frequency;
f
c
= corner frequency;
Minimum tunable frequency = f
max
/256 (D0 thru D7 = 0);
Minimum frequency step (Resolution) = f
max
/256
Data Control Specifications
Data Control Lines
Functions
Latch Strobe (C)
Transition Polarity (P)
Data Control Modes
Mode 1
P = 0; C = 0
P = 0; C = 0
frequency latched on rising edge
P = 1; C = 1
frequency follows input codes
P = 1; C = 1
frequency latched on falling edge
frequency follows input codes
Mode 2
Input Data Levels
(CMOS Logic)
Input Voltage (Vs = 15 Vdc)
Low Level In
High Level In
0 Vdc mn.
11 Vdc mn.
4 Vdc max.
15 Vdc max.
Input Current
High Level In
Low Level In
- 10
-5
μ
Atyp.
+10
-5
μ
Atyp
.
-1
μ
Amax.
.
+1
μ
Amax.
Input Capacitance
5 pF typ
7.5 pF max.
Latch Response
Data Set Up Time
Data Hold Time
Strobe Pulse Width
Input Data Format
1
25 nS
50 nS
80 nS mn.
Frequency Select Bits
Positive Logic
Logic "1" = +Vs
Logic "0" = Gnd
Bit Weighting
D
0
D
7
(Binary-Coded)
LSB (least significant bit)
MSB (most significant bit)
Frequency Range
256 : 1, Binary Weighted
Notes:
1.Frequency data must be present before occurrence of strobe edge.
2.Frequency data must be present after occurrence of strobe edge.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
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| 854L8B-1 | 制造商:FREQUENCYDEVICES 制造商全稱:Frequency Devices, Inc. 功能描述:2" x 4" 4-Pole Filters |
| 854L8B2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
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