參數(shù)資料
型號: 853S314AGILFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: 853S SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
封裝: 4.40 MM X 6.50 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-20
文件頁數(shù): 15/16頁
文件大小: 282K
代理商: 853S314AGILFT
IDT / ICS 3.3V, 2.5V LVPECL/ECL FANOUT BUFFER
8
ICS853S314AFI REV. A JANUARY 24, 2009
ICS853S314I
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
V
CC - 2V
50
Ω
50
Ω
RTT
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
RTT =
Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
125
Ω
125
Ω
84
Ω
84
Ω
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
FIGURE 1B. LVPECL OUTPUT TERMINATION
FIGURE 1A. LVPECL OUTPUT TERMINATION
TERMINATION FOR 3.3V LVPECL OUTPUTS
drive 50
Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion.
Figures 1A and 1B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
INPUTS:
CLKx/nCLKx INPUT:
For applications not requiring the use of the differential input,
both CLKx and nCLKx can be left floating. Though not required,
but for additional protection, a 1k
Ω resistor can be tied from CLKx
to ground.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
APPLICATION INFORMATION
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