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參數(shù)資料
| 型號(hào)： | 853S12AKILFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 853S SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC32 |
| 封裝： | 5 MM X 5 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD-2, VFQFN-32 |
| 文件頁數(shù)： | 2/17頁 |
| 文件大?。?/td> | 328K |
| 代理商： | 853S12AKILFT |
IDT / ICS LVPECL FANOUT BUFFER
10
ICS853S12AKI REV. A MAY 21, 2008
ICS853S12I
LOW SKEW, 1-TO-12, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER
V
CC - 2V
50
Ω
50
Ω
RTT
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
RTT =
Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
125
Ω
125
Ω
84
Ω
84
Ω
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are rec-
ommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50
Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion.
Figures 4A and 4B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FIGURE 4B. LVPECL OUTPUT TERMINATION
FIGURE 4A. LVPECL OUTPUT TERMINATION
TERMINATION FOR 3.3V LVPECL OUTPUTS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 853S12AKIT | 853S SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC32 |
| 853S12AKI | 853S SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC32 |
| 8550D | 1500 mA, 25 V, PNP, Si, SMALL SIGNAL TRANSISTOR, TO-92 |
| 8550C | 1500 mA, 25 V, PNP, Si, SMALL SIGNAL TRANSISTOR, TO-92 |
| 8550SG-E-T92-B | 700 mA, 20 V, PNP, Si, SMALL SIGNAL TRANSISTOR, TO-92 |
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