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參數(shù)資料
| 型號： | 8535AG-21LFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 8535 SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO14 |
| 封裝： | 4.40 X 5 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-14 |
| 文件頁數(shù)： | 14/15頁 |
| 文件大?。?/td> | 835K |
| 代理商： | 8535AG-21LFT |
ICS8535-21
LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
IDT / ICS 3.3V LVPECL FANOUT BUFFER
8
ICS8535AG-21 REV. A FEBRUARY 24, 2009
Application Information
Recommendations for Unused Input and Output Pins
Inputs:
CLK Inputs
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1k
resistor can be tied from the CLK input to ground.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
Outputs:
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and FOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 2A and 2B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
Figure 2A. 3.3V LVPECL Output Termination
Figure 2B. 3.3V LVPECL Output Termination
V
CC - 2V
50
50
RTT
Z
o = 50
Z
o = 50
FOUT
FIN
RTT =
Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
125
125
84
84
Z
o = 50
Z
o = 50
FOUT
FIN
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PDF描述 |
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| 853S12AKILF | 853S SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC32 |
| 853S12AKILFT | 853S SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC32 |
| 853S12AKIT | 853S SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC32 |
| 853S12AKI | 853S SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC32 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 8535AG-21T | 制造商:Integrated Device Technology Inc 功能描述:CLOCK DRVR 2-IN LVPECL 14TSSOP - Tape and Reel |
| 8535AG-31 | 制造商:Integrated Device Technology Inc 功能描述:Clock Driver 2-IN LVPECL 20-Pin TSSOP Tube 制造商:IDT from Components Direct 功能描述:IDT 8535AG-31 CLOCK MANAGEMENT - Rail/Tube 制造商:IDT 功能描述:IDT 8535AG-31 Clock Management |
| 8535AG-31LF | 功能描述:時鐘緩沖器 1:4 LVCMOS-to-3.3V LVPECL Fanout Buffer RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 8535AG-31LFT | 功能描述:時鐘驅(qū)動器及分配 1:4 LVCMOS-to-3.3V LVPECL Fanout Buffer RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| 8535AGI-01 | 制造商:Integrated Device Technology Inc 功能描述:IDT 8535AGI-01 CLOCK MANAGEMENT - Rail/Tube 制造商:Integrated Device Technology Inc 功能描述:IDT 8535AGI-01 Clock Management |
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