參數(shù)資料
型號(hào): 85304AG-01T
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 85304 SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
封裝: 6.50 X 4.40 MM, 0.92 MM PITCH, MO-153, TSSOP-20
文件頁數(shù): 13/15頁
文件大小: 760K
代理商: 85304AG-01T
ICS85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER
IDT / ICS 3.3V LVPECL FANOUT BUFFER
7
ICS85304AG-01 REV. E JULY 8, 2008
Parameter Measurement Information, continued
Output Rise/Fall Time
Application Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how the differential input can be wired to accept
single-ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
Figure 1. Single-Ended Signal Driving Differential Input
20%
80%
20%
tR
t F
VSWING
nQ[0:4]
Q[0:4]
V_REF
Single Ended Clock Input
VCC
CLKx
nCLKx
R1
1K
C1
0.1u
R2
1K
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85304-BK001 制造商:Alpha Wire 功能描述:
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