參數(shù)資料
型號(hào): 84C30A
廠商: LSI Corporation
英文描述: 4-Port Ethernet Controller(四端口以太網(wǎng)控制器)
中文描述: 4端口以太網(wǎng)控制器(四端口以太網(wǎng)控制器)
文件頁數(shù): 1/46頁
文件大小: 439K
代理商: 84C30A
4-Port 84C30A
4-Port
4-1
1
MD400151/C
96339
Ethernet Controller
Features
I
Low Power CMOS Technology
I
4-Port Ethernet Controller Optimized for
Switching Hub, Multiport Bridge/Router,
Server Applications
I
Meets ANSI/IEEE 802.3 and ISO 8802-3 Standards
for Thicknet (10Base-5), Thin Net (10Base-2)
and Twisted Pair (10Base-T)
I
Standard 10MBit/sec Serial Ethernet
I
Selectable Little Endian/Big Endian Transmit Byte
Ordering for FIFO Interface for Intel/Motorola
Compatibility
I
Open Bus Interface
I
Programmability of Double Word Threshold
Count for Space Available/Data Available Ready
Condition for Transmit/Receive FIFO’s
I
Auto Retransmit Upon Collision Sense
I
Preamble Generation and Removal
I
Automatic 32-Bit FCS (CRC) Generation and
Checking
I
Collision Handling, Transmission Deferral and
Retransmission with Automatic Jam and
Backoff Functions
I
Error Interrupt and Status Generation
I
Single 5 V
±
5% Power Supply
I
Standard CPU and Peripheral Interface
Control Signals
I
Independent 128 Byte Transmit/Receive FIFOs
on each Port
- 1 G Bits/sec (133 M Bytes/sec) Peak Data Rate
in 32 Bit Mode.
I
Loopback Capability for Diagnostics
I
32 Bit FIFO Data Path
I
Inputs and Outputs TTL Compatible
I
The Following Additional Features can be
Programmed for the 84C30A
- 64 bit Multicast Filter
- Reports Status of “SQE” During Transmits
- Transmit No CRC Mode
- Transmit No Preamble Mode
- Transmit Packet Autopadding Mode
- Receive CRC Mode
- Disable Self-Receive on Transmits Mode
- Disable Further Transmissions when Both
Transmit Status Registers are Full
- Disable Loading the Transmit Status for
Successfully Transmitted Packets
- Disable the Receive Interrupts Independent
of the Receive Command Register Setting
I
Transmit Status on a Per Packet Basis Reports the
Following
- Occurrence of a Transmit FIFO Underflow
- Transmit Collision Occurrence
- 16 Collision Occurrence
- Carrier Sense Error During Transmission
- 10 Mbit/sec Transmit Clock Detect
- Late Collision Occurrence
- Transmission Successful
- Transmission Deferred
I
Each Port Includes the Following Counters or
Status Bits for Network Management Statistics
- 16 Bit Short Receive Frame Counter
- 16 Bit Alignment Error Counter
- 16 Bit CRC Error Counter
- 8 Bit Oversize Receive Frame Counter
- 16 Bit Transmit Collision Counter
- 16 Bit Total Collision Counter
- Transmit Status Bits for “Carrier” and
“SQE” During Transmits
I
Full Duplex Operation
- Provides 20 Mbps Bandwidth for Switched
Networks
- Supports AutoDUPLEX Mode for Automatic
Full Duplex Operation
I
208 Pin PQFP package
Full Duplex
Note: Check for latest Data Sheet revision
before starting any designs.
SEEQ Data Sheets are now on the Web, at
www.lsilogic.com.
This document is an LSI Logic document. Any
reference to SEEQ Technology should be
considered LSI Logic.
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