參數(shù)資料
型號(hào)： 8406702RA
廠(chǎng)商： INTERSIL CORP
元件分類(lèi)： 通用總線(xiàn)功能
英文描述： CMOS Octal Latching Inverting Bus Driver
中文描述： CMOS SERIES, 8-BIT DRIVER, INVERTED OUTPUT, CDIP20
封裝： CERAMIC, DIP-20
文件頁(yè)數(shù)： 1/6頁(yè)
文件大?。?/td> 105K
代理商： 8406702RA
4-281
March 1997
82C83H
CMOS Octal Latching Inverting Bus Driver
Features
Full 8-Bit Parallel Latching Buffer
Bipolar 8283 Compatible
Three-State Inverting Outputs
Propagation Delay . . . . . . . . . . . . . . . . . . . . . .25ns Max
Gated Inputs
- Reduce Operating Power
- Eliminate the Need for Pull-Up Resistors
Single 5V Power Supply
Low Power Operation
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
Operating Temperature Ranges
- C82C83H . . . . . . . . . . . . . . . . . . . . . . . . .0
o
C to +70
o
C
- I82C83H. . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
- M82C83H. . . . . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Description
The Intersil 82C83H is a high performance CMOS Octal
Latching Buffer manufactured using a self-aligned silicon gate
CMOS process (Scaled SAJI IV). The 82C83H provides an 8-
bit parallel latch/buffer in a 20 lead pin package. The active
high strobe (STB) input allows transparent transfer of data
and latches data on the negative transition of this signal. The
active low output enable (OE) permits simple interface to
microprocessor systems. The 82C83H provides inverted data
at the outputs.
Ordering Information
Pinouts
82C83H (PDIP, CERDIP)
TOP VIEW
82C83H (PLCC, CLCC)
TOP VIEW
PART NO.
CP82C83H
IP82C83H
CS82C83H
IS82C83H
CD82C83H
ID82C83H
MD82C83H/B
8406702RA
MR82C83H/B
84067022A
PACKAGE
20 Ld PDIP
TEMP RANGE
0
o
C to +70
o
C
-40
o
C to +85
o
C
0
o
C to +70
o
C
-40
o
C to +85
o
C
0
o
C to +70
o
C
-40
o
C to +85
o
C
0
o
C to +70
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
PKG. NO
E20.3
E20.3
N20.35
N20.35
F20.3
F20.3
F20.3
F20.3
J20.A
J20.A
20 Ld PLCC
20 Ld CERDIP
SMD#
20 Pad CLCC
SMD#
TRUTH TABLE
OE
H
L
L
L
STB
X
H
H
↓
DI
X
L
H
X
DO
HI-Z
H
L
H = Logic One
L = Logic Zero
X = Don‘t Care
HI-Z = High Impedance
↓
= Negative Transition
= Latched to Value of Last
Data
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
DI
0
DI
1
DI
2
DI
3
DI
4
DI
5
DI
6
DI
7
OE
GND
V
CC
DO
0
DO
1
DO
2
DO
3
DO
4
DO
5
DO
6
DO
7
STB
PIN NAMES
PIN
DESCRIPTION
DI
0
- DI
7
DO
0
- DO
7
STB
Data Input Pins
Data Output Pins
Active High Strobe
OE
Active Low Output Enable
19
3
2
20
1
15
16
17
18
14
9
10
11
12
13
4
5
6
7
8
DI
4
DI
5
DI
6
DI
7
DI
3
O
G
S
D
7
D
6
DO
2
DO
3
DO
4
DO
5
DO
1
D
2
D
1
D
0
V
C
D
0
File Number
2971.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
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