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參數(shù)資料
| 型號： | 840002AL |
| 英文描述： | FEMTOCLOCKS⑩ CRYSTAL-TO LVCMOS/ |
| 中文描述： | FEMTOCLOCKS⑩晶體到的LVCMOS / |
| 文件頁數(shù)： | 10/13頁 |
| 文件大小： | 204K |
| 代理商： | 840002AL |
Integrated
Circuit
Systems, Inc.
840002AGI
www.icst.com/products/hiperclocks.html
REV. A MARCH 10, 2005
10
ICS840002I
F
EMTO
C
LOCKS
C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
L
AYOUT
G
UIDELINE
Figure 3 shows a schematic example of the ICS840002I. An
example of LVCMOS termination is shown in this schematic.
Additional LVCMOS termination approaches are shown in the
LVCMOS Termination Application Note. In this example, an 18
pF parallel resonant 26.5625MHz crystal is used. The C1=22pF
F
IGURE
3. ICS840002I S
CHEMATIC
E
XAMPLE
and C2=22pF are recommended for frequency accuracy. For
different board layout, the C1 and C2 may be slightly adjusted
for optimizing frequency accuracy. 1K
Ω
pullup or pulldown re-
sistors can be used for the logic control input pins.
XTAL1
Optional Termination
RD1
RU1
1K
VDD
C4
0.01u
If not using the crystal input, it can be left floating.
For additional protection the XTAL_IN pin can be
tied to ground.
Zo = 50 Ohm
LVCMOS
Set Logic
Input to
'0'
Unused output can be left floating. There should
no trace attached to unused output. Device
characterized with all outputs terminated.
R1
10
R4
To Logic
Input
pins
Set Logic
Input to
'1'
Logic Control Input Examples
R2
33
C6
0.1u
VDDA
C2
22pF
To Logic
Input
pins
Zo = 50 Ohm
X1
VDD
RD2
1K
C5
0.1u
C3
10uF
VDD
R3
VDD
LVCMOS
XTAL2
U1
ICS840002i
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FSEL0
XTAL_SEL
TEST_CLK
VDDA
VDD
XTAL_OUT
XTAL_IN
VDQ1
Q0
GND
GND
FSEL1
RU2
VDD
C1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 840002AG | FEMTOCLOCKS⑩ CRYSTAL-TO LVCMOS/ |
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| 84001012C | Octal D-Type Flip-Flop |
| 84001012X | Octal D-Type Flip-Flop |
| 8400101RA | Octal D-Type Flip-Flop |
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