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參數(shù)資料
| 型號： | 83F6096 |
| 英文描述： | IC-LED DISPLAY DRIVER |
| 中文描述： | 集成電路，LED顯示驅(qū)動器 |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 137K |
| 代理商： | 83F6096 |
Micrel
MIC5800/5801
Electrical Characteristics:
at T
A
= +25
°
C, V
DD
= 5V (unless otherwise noted)
8-14
Limits
Typ.
Characteristic
Output Leakage Current
Symbol
I
CEX
Test Conditions
V
CE
= 50 V, T
A
= +25
°
C
V
CE
= 50 V, T
A
= +70
°
C
I
C
= 100 mA
I
C
= 200 mA
I
C
= 350 mA, V
DD
= 7.0 V
Min.
Max.
50
100
1.1
1.3
1.6
1.0
Units
μ
A
Collector-Emitter
Saturation Voltage
V
CE(SAT)
0.9
1.1
1.3
V
Input Voltage
V
IN(0)
V
IN(1)
V
V
DD
= 12 V
V
DD
= 10 V
V
DD
= 5.0 V (See Note)
V
DD
= 12 V
V
DD
= 10 V
V
DD
= 5.0 V
V
DD
= 12 V, Outputs Open
V
DD
= 10 V, Outputs Open
V
DD
= 5.0 V, Outputs Open
V
DD
= 12 V, Outputs Open, Inputs = 0 V
V
DD
= 5.0 V, Outputs Open, Inputs = 0 V
V
R
= 50 V, T
A
= +25
°
C
V
R
= 50 V, T
A
= +70
°
C
I
F
= 350 mA
10.5
8.5
3.5
50
50
50
Input Resistance
R
IN
200
300
600
1.0
0.9
0.7
k
Supply Current
I
DD(ON)
(Each
Stage)
I
DD(OFF)
(Total)
I
R
2.0
1.7
1.0
200
100
50
100
2.0
mA
μ
A
50
Clamp Diode
Leakage Current
Clamp Diode Forward Voltage
μ
A
V
F
1.7
V
NOTE :
Operation of these devices with standard TTL or DTL may require the use of appropriate pull-up resistors to insure a minimum logic “1”.
CLEAR
F
STROBE
OUTPUT
ENABLE
IN
C
B
A
G
N
E
C
B
A
G
D
C
B
E
OUTN
Timing Conditions
(Logic Levels are V
DD
and Ground)
A.
B.
C.
D.
E.
F.
G.
Minimum data active time before strobe enabled (data set-up time) ......................................................................50 ns
Minimum data active time after strobe disabled (data hold time)............................................................................ 50 ns
Minimum strobe pulse width ................................................................................................................................. 125 ns
Typical time between strobe activation and output on to off transition..................................................................500 ns
Typical time between strobe activation and output off to on transition..................................................................500 ns
Minimum clear pulse width ................................................................................................................................... 300 ns
Minimum data pulse width .................................................................................................................................... 225 ns
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