參數(shù)資料
型號: 83C196MD
廠商: Intel Corp.
英文描述: 1MSPS, 12-Bit ADC in 6 Lead SOT-23; Package: SOT-23; No of Pins: 6; Temperature Range: Commercial
中文描述: 8XC196MH工業(yè)電機(jī)控制CHMOS單片機(jī)
文件頁數(shù): 7/22頁
文件大?。?/td> 1363K
代理商: 83C196MD
8XC196KB/8XC196KB16
PIN DESCRIPTIONS
(Continued)
Symbol
Name and Function
Port 0
8-bit high impedance input-only port. Three pins can be used as digital inputs and/or as
analog inputs to the on-chip A/D converter.
Port 1
8-bit quasi-bidirectional I/O port. These pins are shared with HOLD, HLDA and BREQ.
Port 2
8-bit multi-functional port. All of its pins are shared with other functions in the 87C196KB.
Pins P2.6 and P2.7 are quasi-bidirectional.
Ports 3 and 4
8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus, which has strong internal pullups.
HOLD
Bus Hold input requesting control of the bus. Enabled by setting WSR.7.
HLDA
Bus Hold acknowledge output indicating release of the bus. Enabled by setting WSR.7.
BREQ
Bus Request output activated when the bus controller has a pending external memory
cycle. Enabled by setting WSR.7.
TxD
The TxD pin is used for serial port transmission in Modes 1, 2 and 3. In Mode 0 the pin is
used as the serial clock output.
RxD
Serial Port Receive pin used for serial port reception. In Mode 0 the pin functions as input or
output data.
EXTINT
A rising edge on the EXTINT pin will generate an external interrupt.
T2CLK
The T2CLK pin is the Timer2 clock input or the serial port baud rate generator input.
T2RST
A rising edge on the T2RST pin will reset Timer2.
PWM
The pulse width modulator output.
T2UP-DN
The T2UPDNpin controls the direction of Timer2 as an up or down counter.
T2CAPTURE
A rising edge on P2.7 will capture the value of Timer2 in the T2CAPTUREregister.
PMODE
ProgrammingMode Select. Determines the EPROM programming algorithm that is
performed. PMODEis sampled after a chip reset and should be static while the part is
operating.
SID
Slave ID Number. Used to assign each slave a pin of Port 3 or 4 to use for passing
programming verification acknowledgement.
PALE
ProgrammingALE Input. Accepted by the 87C196KB when it is in Slave Programming
Mode. Used to indicate that Ports 3 and 4 contain a command/address.
PROG
Programming.Falling edge indicates valid data on PBUSand the beginning of
programming. Rising edge indicates end of programming.
PACT
ProgrammingActive. Used in the Auto ProgrammingMode to indicate when programming
activity is complete.
PVAL
Program Valid. This signal indicates the success or failure of programming in the Auto
ProgrammingMode. A zero indicates successful programming.
PVER
Program Verification. Used in Slave Programmingand Auto CLB ProgrammingModes.
Signal is low after rising edge of PROGif the programming was not successful.
AINC
Auto Increment. Active low signal indicates that the auto increment mode is enabled. Auto
Increment will allow reading or writing of sequential EPROM locations without address
transactions across the PBUSfor each read or write.
Ports 3
and 4
(Programming
Mode)
Address/Command/Data Bus. Used to pass commands, addresses, and data to and from
slave mode 87C196KBs. Used by chips in Auto ProgrammingMode to pass command,
addresses and data to slaves. Also used in the Auto ProgrammingMode as a regular
system bus to access external memory. Should have pullups to V
CC
when used in slave
programming mode.
7
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