參數(shù)資料
型號: 83C196LD
廠商: Intel Corp.
英文描述: CHMOS 16-Bit Microcontroller(CHMOS型 16位微控制器)
中文描述: CHMOS 16位微控制器(CHMOS型16位微控制器)
文件頁數(shù): 1/22頁
文件大?。?/td> 289K
代理商: 83C196LD
ADVANCE INFORMATION
COPYRIGHT INTEL CORPORATION,
1998
May 1998
Order Number: 272805-002
83C196LD
CHMOS 16-BIT MICROCONTROLLER
Automotive
NOTE
This document contains information on products in the sampling and initial production
phases of development. The specifications are subject to change without notice. Verify
with your local Intel sales office that you have the latest datasheet before finalizing a
design.
The
83C196LD
is a low-cost, pin-compatible replacement for the existing 87C196JR. This product features
an enhanced synchronous serial I/O (SSIO) port for more flexible communication to other devices. The
enhanced SSIO is compatible with Motorola’s Serial Peripheral Interface (SPI) protocol and National’s
Microwire protocol. To optimize die size, the A/D converter was removed for use in those applications that
use an off-chip A/D converter.
The MCS
96 microcontroller family members are all high-performance microcontrollers with 16-bit CPUs.
The
83C196LD
is
composed
of
a
high-speed
asynchronous/synchronous serial I/O port (8096 compatible) with a dedicated 16-bit baud-rate generator; an
additional synchronous serial I/O port with full duplex master/slave transceivers; a flexible timer/counter
structure with prescaler, cascading, and quadrature capabilities; six modularized, multiplexed high-speed I/O
for capture and compare (called event processor array) with 200 ns resolution and double buffered inputs;
and a sophisticated, prioritized interrupt structure with programmable peripheral transaction server (PTS).
core
with
the
following
peripherals:
an
I
22 MHz operation
I
16 Kbytes of on-chip ROM
I
384 bytes of on-chip register RAM
I
Register-to-register architecture
I
Peripheral transaction server (PTS)
with high-speed, microcoded interrupt
service routines
I
Full-duplex serial I/O port with
dedicated baud-rate generator
I
Enhanced full-duplex, synchronous
serial I/O port (SSIO)
I
High-speed event processor array
— Six capture/compare channels
— Two compare-only channels
— Two 16-bit software timers
I
Programmable 8- or 16-bit external bus
I
Design enhancements for EMI
reduction
I
Oscillator failure detection circuitry
I
SFR register that indicates the source
of the last reset
I
Watchdog timer (WDT)
I
Cost reduced replacement for the
87C196JR
I
40° C to
+
125° C ambient temperature
I
52-pin PLCC package
相關(guān)PDF資料
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