2010-2012 Peregrine Semiconductor Corp. All rights reserved.
參數(shù)資料
型號(hào)： 83336-22
廠商： Peregrine Semiconductor
文件頁(yè)數(shù)： 3/12頁(yè)
文件大?。?/td> 0K
描述： IC PLL INTEGER-N 3GHZ 44CQFJ
標(biāo)準(zhǔn)包裝： 500
系列： UltraCMOS™
類型： 時(shí)鐘緩沖器/驅(qū)動(dòng)器，多路復(fù)用器
PLL： 是
主要目的： 軍事應(yīng)用
輸入： 時(shí)鐘
輸出： 時(shí)鐘
電路數(shù)： 1
比率 - 輸入:輸出： 1:1
差分 - 輸入:輸出： 是/無(wú)
頻率 - 最大： 3GHz
電源電壓： 2.85 V ~ 3.15 V
工作溫度： -55°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 44-CLCC 裸露焊盤
供應(yīng)商設(shè)備封裝： 44-CQFJ（16.51x16.51）
包裝： 帶卷 (TR)
其它名稱： PE83336
Product Specification
PE83336
Page 11 of 12
Document No. 70-0137-05 │ www.psemi.com
2010-2012 Peregrine Semiconductor Corp. All rights reserved.
PD_U and PD_D drive an active loop filter which
controls the VCO tune voltage. PD_U pulses
result in an increase in VCO frequency; PD_D
pulses result in a decrease in VCO frequency (for
a positive Kv VCO).
A lock detect output, LD is also provided, via the
pin Cext. Cext is the logical “NAND” of PD_
U and
PD_
D waveforms, which is driven through a series
2 k
Ω resistor. Connecting Cext to an external
shunt capacitor provides low pass filtering of this
signal. Cext also drives the input of an internal
inverting comparator with an open drain output.
Thus LD is an “AND” function of PD_
U and PD_D.
Enhancement Register
The functions of the enhancement register bits are shown below with all bits active “high”.
Table 9. Enhancement Register Bit Functionality
** Program to 0
Phase Detector
The phase detector is triggered by rising edges
from the main Counter (fp) and the reference
counter (fc). It has two outputs, PD_U, and PD_D.
If the divided VCO leads the divided reference in
phase or frequency (fp leads fc), PD_D pulses
“l(fā)ow”. If the divided reference leads the divided
VCO in phase or frequency (fc leads fp), PD_U
pulses “l(fā)ow”. The width of either pulse is directly
proportional to phase offset between the two input
signals, fp and fc.
The phase detector gain is equal to 2.7 V / 2 π,
which numerically yields 0.43 V / radian.
Bit Function
Description
Bit 0
Reserved**
Bit 1
Reserved**
Bit 2
Reserved**
Bit 3
Power down
Power down of all functions except programming interface.
Bit 4
Counter load
Immediate and continuous load of counter programming as directed by the
Bmode and
Smode inputs.
Bit 5
MSEL output
Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.
Bit 6
Prescaler output
Drives the raw internal prescaler output onto the Dout output.
Bit 7
fp, fc
OE
fp, fc outputs disabled.
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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