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Intel 450NX PCIset
CONTENTS
3.2.2
MIOC Configuration Space .......................................................................................................................... 3-3
3.3.1
BUFSIZ: Buffer Sizes ................................................................................................................... 3-4
3.3.2
BUSNO[1:0]: Lowest PCI Bus Number, per PXB ......................................................................... 3-5
3.3.3
CHKCON: Check Connection ....................................................................................................... 3-5
3.3.4
CLASS: Class Code Register ....................................................................................................... 3-6
3.3.5
CONFIG: Software-Defined Configuration Register ..................................................................... 3-6
3.3.6
CVCR: Configuration Values Captured on Reset ......................................................................... 3-8
3.3.7
CVDR: Configuration Values Driven On Reset ............................................................................ 3-9
3.3.8
DBC[15:0]: DRAM Bank Configuration Registers ......................................................................... 3-9
3.3.9
DEVMAP: System Bus PCI Device Map .................................................................................... 3-10
3.3.10
DID: Device Identification Register ............................................................................................. 3-11
3.3.11
ECCCMD: ECC Command Register .......................................................................................... 3-11
3.3.12
ECCMSK: ECC Mask Register ................................................................................................... 3-12
3.3.13
ERRCMD: Error Command Register .......................................................................................... 3-12
3.3.14
ERRSTS: Error Status Register ................................................................................................. 3-13
3.3.15
GAPEN: Gap Enables ................................................................................................................ 3-14
3.3.16
HDR: Header Type Register ....................................................................................................... 3-15
3.3.17
HEL[1:0] Host Bus Error Log ...................................................................................................... 3-15
3.3.18
HXGB: High Expansion Gap Base ............................................................................................. 3-16
3.3.19
HXGT: High Expansion Gap Top ............................................................................................... 3-16
3.3.20
IOABASE: I/O APIC Base Address ............................................................................................ 3-16
3.3.21
IOAR: I/O APIC Ranges ............................................................................................................. 3-17
3.3.22
IOR: I/O Ranges ......................................................................................................................... 3-17
3.3.23
ISA: ISA Space ........................................................................................................................... 3-18
3.3.24
LXGB: Low Expansion Gap Base ............................................................................................... 3-18
3.3.25
LXGT: Low Expansion Gap Top ................................................................................................. 3-18
3.3.26
MAR[6:0]: Memory Attribute Region Registers ........................................................................... 3-19
3.3.27
MEA[1:0] Memory Error Effective Address ................................................................................. 3-20
3.3.28
MEL[1:0] Memory Error Log ....................................................................................................... 3-20
3.3.29
MMBASE: Memory-Mapped PCI Base ...................................................................................... 3-21
3.3.30
MMR[3:0]: Memory-Mapped PCI Ranges .................................................................................. 3-21
3.3.31
PMD[1:0]: Performance Monitoring Data Register ..................................................................... 3-21
3.3.32
PME[1:0]: Performance Monitoring Event Selection .................................................................. 3-22
3.3.33
PMR[1:0]: Performance Monitoring Response ........................................................................... 3-23
3.3.34
RC: Reset Control Register ........................................................................................................ 3-24
3.3.35
RCGP: RCGs Present ................................................................................................................ 3-25
3.3.36
REFRESH: DRAM Refresh Control Register ............................................................................. 3-25
3.3.37
RID: Revision Identification Register .......................................................................................... 3-25
3.3.38
ROUTE[1:0]: Route Field Seed ................................................................................................. 3-26
3.3.39
SMRAM: SMM RAM Control Register ........................................................................................ 3-26
3.3.40
SUBA[1:0]: Bus A Subordinate Bus Number, per PXB .............................................................. 3-27
3.3.41
SUBB[1:0]: Bus B Subordinate Bus Number, per PXB .............................................................. 3-28
3.3.42
TCAP[0:3]: Target Capacity, per PXB/PCI Port .......................................................................... 3-28
3.3.43
TOM: Top of Memory ................................................................................................................. 3-29
3.3.44
VID: Vendor Identification Register ............................................................................................ 3-29
PXB Configuration Space .......................................................................................................................... 3-29
3.4.1
BUFSIZ: Buffer Sizes ................................................................................................................. 3-31
3.4.2
CLASS: Class Code Register ..................................................................................................... 3-31
3.4.3
CLS: Cache Line Size ................................................................................................................ 3-32
3.4.4
CONFIG: Configuration Register ................................................................................................ 3-32
3.4.5
DID: Device Identification Register ............................................................................................. 3-33
3.4.6
ERRCMD: Error Command Register .......................................................................................... 3-34
3.4.7
ERRSTS: Error Status Register ................................................................................................. 3-35
CONFIG_DATA: Configuration Data Register .............................................................................. 3-2
3.3
3.4