
82077AA CHMOS Single-Chip Floppy Disk Controller
CONTENTS
PAGE
1.0 INTRODUCTION
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1.1 Oscillator
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1.2 Perpendicular Recording Mode
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2.0 MICROPROCESSOR INTERFACE
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2.1 Status, Data, and Control
Registers
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2.1.1a Status Register A
(SRA, PS/2 Mode)
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2.1.1b Status Register A
(SRA, Model 30 Mode)
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2.1.2a Status Register B
(SRB, PS/2 Mode)
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2.1.2b Status Register B
(SRB, Model 30 Mode)
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2.1.3 Digital Output Register
(DOR)
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2.1.4 Tape Drive Register (TDR)
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2.1.5 Datarate Select Register
(DRS)
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2.1.6 Main Status Register
(MSR)
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2.1.7 FIFO (Data)
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2.1.8a Digital Input Register
(DIR, PC-AT Mode)
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2.1.8b Digital Input Register
(DIR, PS/2 Mode)
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2.1.8c Digital Input Register
(DIR, Model 30 Mode)
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2.1.9a Configuration Control
Register
(CCR, PC AT and PS/2 Modes)
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2.1.9b Configuration Control
Register
(CCR, Model 30 Mode)
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2.2 RESET
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2.2.1 Reset Pin (‘‘Hardware’’)
Reset
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2.2.2 DOR Reset vs DSR Reset
(‘‘Software’’ Reset)
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CONTENTS
2.3 DMA Transfers
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PAGE
3.0 DRIVE INTERFACE
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3.1 Cable Interface
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3.2 Data Separator
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3.2.1 Jitter Tolerance
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3.2.2 Locktime (t
LOCK
)
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3.2.3 Capture Range
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3.2.4 Reference Filter
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3.3 Write Precompensation
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4.0 CONTROLLER PHASES
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4.1 Command Phase
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4.2 Execution Phase
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4.2.1 Non-DMA Mode, Transfers
from the FIFO to the Host
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4.2.2 Non-DMA Mode, Transfers
from the Host to the FIFO
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4.2.3 DMA Mode, Transfers from
the FIFO to the Host
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4.2.4 DMA Mode, Transfers from
the Host to the FIFO
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4.2.5 Data Transfer Termination
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4.3 Result Phase
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5.0 COMMAND SET/DESCRIPTIONS
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5.1 Data Transfer Commands
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5.1.1 Read Data
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5.1.2 Read Deleted Data
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5.1.3 Read Track
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5.1.4 Write Data
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5.1.5 Write Deleted Data
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5.1.6 Verify
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5.1.7 Format Track
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5.1.7.1 Format Fields
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5.1.8 Scan Commands
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