參數(shù)資料
型號： 81C56
廠商： Intersil Corporation
英文描述： Radiation Hardened 256 x 8 CMOS RAM
中文描述： 輻射硬化256 × 8 CMOS存儲器
文件頁數(shù)： 1/14頁
文件大?。?/td> 86K
代理商： 81C56
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
HS-81C55RH,
HS-81C56RH
Radiation Hardened
256 x 8 CMOS RAM
Features
Devices QML Qualified in Accordance with
MIL-PRF-38535
Detailed Electrical and Screening Requirements are
Contained in SMD# 5962-95818 and Intersil’ QM Plan
Radiation Hardened EPI-CMOS
- Parametrics Guaranteed 1 x 10
5
RAD(Si)
- Transient Upset > 1 x 10
8
RAD(Si)/s
- Latch-Up Free > 1 x 10
12
RAD(Si)/s
Electrically Equivalent to Sandia SA 3001
Pin Compatible with Intel 8155/56
Bus Compatible with HS-80C85RH
Single 5V Power Supply
Low Standby Current 200
μ
A Max
Low Operating Current 2mA/MHz
Completely Static Design
Internal Address Latches
Two Programmable 8-Bit I/O Ports
One Programmable 6-Bit I/O Port
Programmable 14-Bit Binary Counter/Timer
Multiplexed Address and Data Bus
Self Aligned Junction Isolated (SAJI) Process
Military Temperature Range -55
o
C to +125
o
C
Description
The HS-81C55/56RH are radiation hardened RAM and I/O
chips fabricated using the Intersil radiation hardened Self-
Aligned Junction Isolated (SAJI) silicon gate technology.
Latch-up free operation is achieved by the use of epitaxial
starting material to eliminate the parasitic SCR effect seen in
conventional bulk CMOS devices.
The HS-81C55/56RH is intended for use with the
HS-80C85RH radiation hardened microprocessor system. The
RAM portion is designed as 2048 static cells organized as 256
x 8. A maximum post irradiation access time of 500ns allows
the HS-81C55/56RH to be used with the HS-80C85RH CPU
without any wait states. The HS-81C55RH requires an active
low chip enable while the HS-81C56RH requires an active high
chip enable. These chips are designed for operation utilizing a
single 5V power supply.
Functional Diagram
256 x 8
STATIC
RAM
A
B
C
TIMER
IO/M
AD0 - AD7
CE OR CE
ALE
RD
WR
RESET
TIMER CLK
TIMER OUT
8
PA0 - PA7
PORT A
8
PB0 - PB7
PORT B
8
PC0 - PC5
PORT C
VDD (10V)
GND
81C55RH = CE
81C56RH = CE
Ordering Information
PART NUMBER
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
SCREENING LEVEL
PACKAGE
5962R9XXXX01QRC
MIL-PRF-38535 Level Q
40 Lead SBDIP
5962R9XXXX01VRC
MIL-PRF-38535 Level V
40 Lead SBDIP
5962R9XXXX01QXC
MIL-PRF-38535 Level Q
42 Lead Ceramic Flatpack
5962R9XXXX01VXC
MIL-PRF-38535 Level V
42 Lead Ceramic Flatpack
5962R9XXXX02QRC
MIL-PRF-38535 Level Q
40 Lead SBDIP
5962R9XXXX02VRC
MIL-PRF-38535 Level V
40 Lead SBDIP
5962R9XXXX02QXC
MIL-PRF-38535 Level Q
42 Lead Ceramic Flatpack
5962R9XXXX02VXC
MIL-PRF-38535 Level V
42 Lead Ceramic Flatpack
HS1-81C55RH/Sample
Sample
40 Lead SBDIP
HS9-81C55RH/Sample
Sample
42 Lead Ceramic Flatpack
HS1-81C56RH/Sample
Sample
40 Lead SBDIP
HS9-81C56RH/Sample
Sample
42 Lead Ceramic Flatpack
Spec Number
518056
File Number
3039.1
March 1996
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