參數(shù)資料
型號(hào): 80L960JF
廠商: Intel Corp.
英文描述: 3.3 V Embedded 32-Bit Microprocessor(3.3 V 嵌入式 32位微處理器)
中文描述: 3.3伏嵌入式32位微處理器(3.3伏嵌入式32位微處理器)
文件頁(yè)數(shù): 1/59頁(yè)
文件大?。?/td> 392K
代理商: 80L960JF
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any
patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Information
contained herein supersedes previously published specifications on these devices from Intel.
INTEL CORPORATION, 1995
September 1995
Order Number: 272744-002
A
PRELIMINARY
80L960JA/JF
3.3 V EMBEDDED 32-BIT MICROPROCESSOR
3.3 Volt Version of the 80960JA/JF Processor
I
Pin/Code Compatible with all 80960Jx
Processors
I
High-Performance Embedded Architecture
— One Instruction/Clock Execution
— Load/Store Programming Model
— Sixteen 32-Bit Global Registers
— Sixteen 32-Bit Local Registers (8 sets)
— Nine Addressing Modes
— User/Supervisor Protection Model
I
Two-Way Set Associative Instruction Cache
— 80L960JA - 2 Kbyte
— 80L960JF - 4 Kbyte
— Programmable Cache Locking
Mechanism
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Direct Mapped Data Cache
— 80L960JA - 1 Kbyte
— 80L960JF - 2 Kbyte
— Write Through Operation
I
On-Chip Stack Frame Cache
— Seven Register Sets Can Be Saved
— Automatic Allocation on Call/Return
— 0-7 Frames Reserved for High-Priority
Interrupts
I
On-Chip Data RAM
— 1 Kbyte Critical Variable Storage
— Single-Cycle Access
Figure 1. 80L960JA/JF Microprocessor
I
High Bandwidth Burst Bus
— 32-Bit Multiplexed Address/Data
— Programmable Memory Configuration
— Selectable 8-, 16-, 32-Bit Bus Widths
— Supports Unaligned Accesses
— Big or Little Endian Byte Ordering
I
New Instructions
— Conditional Add, Subtract and Select
— Processor Management
I
High-Speed Interrupt Controller
— 31 Programmable Priorities
— Eight Maskable Pins plus NMI
— Up to 240 Vectors in Expanded Mode
I
Two On-Chip Timers
— Independent 32-Bit Counting
— Clock Prescaling by 1, 2, 4 or 8
— lnternal Interrupt Sources
I
Halt Mode for Low Power
I
IEEE 1149.1 (JTAG) Boundary Scan
Compatibility
I
Packages
— 132-Lead Pin Grid Array (PGA)
— 132-Lead Plastic Quad Flat Pack (PQFP)
PIN 1
132
99
66
33
i960
i
i
M
19xx
M
19xx
A
A80L960Jx
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NG80L960Jx
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