參數(shù)資料
型號: 80KSBR200
廠商: Integrated Device Technology, Inc.
英文描述: sRIO SERIAL BUFFER FLOW-CONTROL DEVICE
中文描述: sRIO的串行緩沖器流量控制裝置
文件頁數(shù): 1/172頁
文件大?。?/td> 1302K
代理商: 80KSBR200
1 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.
NOT AN OFFER FOR SALE
The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
Devic e Overview
The IDT80KSBR200 is a high speed Serial Buffer (SerB) that can
connect to any Serial RapidIO compliant interface. This device is built to
work with any sRIO device and especially with the IDT Pre-Processing
Switch (PPS), IDT70K200. The SerB performs buffering and off-loading
of data as well as buffer-delay of data samples in various environments.
This device primarily acts as an master in which the SerB bursts data to
a programmed memory location once some criteria have been meet.
This combination of storage and flexibility make it the perfect buffering
solution for sRIO systems.
Features
Serial RapidIO Port
Interface - sRIO
One four-lane (4x) link, configurable to one-lane (1x) link
Port Speeds selectable: 3.125 Gbps, 2.5 Gbps, or 1.25 Gbps
Short haul or long haul reach for each PHY speed
Support 8-bit and 16-bit deviceID
Error management supports standard
sRIO version 1.3
Class 1+ End Point Device
10 Gbps Throughput
18Mbit Internal Density
Programmable Target Address
Packet Tally Indicator
Packet Interval Timer
Replace Missing Packet
Optional External QDR SRAMAvailable
Up to 72Mbit external QDR SRAM
QDR SRAM 200 MHz; (18M 36M, 72M)
Seamless Integration of Internal and External Memory
Internal and external memory functions as a single buffer
Single Port Buffering
Status Flags for Combined Internal/External Memories
Full, Empty, Partially Empty, Partially Full
Direct or polled operation of flag status bus
Optional Watermark
Serial Buffer can Either Send a Flag or Transmt Data at a Specific Packet
Count
Interface - I
2
C Interface Port
One I
2
C port for maintenance and error reporting
Interface - JTAG Interface
JTAG Functionality for boundary scan and programmng
High-Speed CMOS Technology
1.2V Core operation with 3.3/2.5V JTAG interface
Package: 484-pin Plastic Ball Grid Array
23mmx 23mm 1.0mmball pitch
Advanced Datasheet
80KSBR200
sRIO SERIAL BUFFER
FLOW-CONTROL DEVICE
TCK
TMS
TDI
TDO
SCL
SDA
J
I
D
O
S
1x/4x sRIO
Interface
S
3
3
CQ
CQ
K/K
A
Q
D
S-Port 1
P-Port
drw01 DSC-6730
Hardwire
Config
2
2
Rd Wr
QDR Clk
2
FR
PHY Clk
Flags
F
2
8
I
F
F
M
MR
I
2
C
Configuration
and
Flag Registers
M
Queue 0
18 Mbits
Block Diagram
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