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參數(shù)資料
| 型號： | 7P640ATA2503C25 |
| 英文描述： | Flash Memory Card(640M位閃速存儲器卡) |
| 中文描述： | 閃存卡（640M的位閃速存儲器卡） |
| 文件頁數(shù)： | 13/62頁 |
| 文件大?。?/td> | 626K |
| 代理商： | 7P640ATA2503C25 |
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7PxxxATA25xxC25
June 2000 Rev. 1 – ECO #12936
13
White Electronic Designs Corporation
(508) 366-5151
2. Configuration and Status Register (Address 202H)
This register is used for observing the card state.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CHGED
SIGCHG
IOIS8
0
0
PWD
INTR
0
Note: initial value: 00H
Name
R/W
Function
CHGED
(CARD->)
R
This bit indicates that the CRDY/-BSY bit on the Pin Replacement register is set to "1".
When CHGED bit is set to "1", the -STSCHG pin is held "L" at the condition of SIGCHG
bit set to "1" and the card configured for the I/O interface.
SIGCHG
(HOST->)
R/W
This bit is set or reset by the host for enabling and disabling the status-change signal (-
STSCHG pin). When the card is configured I/O card interface and this bit is set to "1", -
STSCHG pin is controlled by the CHGED bit. If this bit is set to "0", the -STSCHG pin is
kept "H".
IOIS8
(HOST->)
R/W
The host sets this field to "1" when it can provide I/O cycles only with on 8 bit data bus
(D7 to D0).
PWD
(HOST->)
R/W
When this bit is set to "1", the card enters the sleep state (Power Down mode). When
this bit is reset to "0", the card transfers to the idle state (active mode). RRDY/-BSY bit
on the Pin Replacement Register becomes BUSY when this bit is changed. RRDY/-
BSY will not become Ready until the power state requested has been entered. This
card automatically powers down when it is idle, and powers back up when it receives a
command.
INTR
(CARD->)
R
This bit indicates the internal state of the interrupt request. This bit state is available
whether the I/O card interface has been configured or not. This signal remains true until
the condition which caused the interrupt request has been serviced. If interrupts are
disabled by the -IEN bit in the Device Control Register, this bit is a zero.
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