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| 型號： | 7P512FLG0801I15 |
| 英文描述： | Peripheral Miscellaneous |
| 中文描述： | 周邊雜項 |
| 文件頁數(shù)： | 11/13頁 |
| 文件大?。?/td> | 125K |
| 代理商： | 7P512FLG0801I15 |
August 2000 Rev. 3 - ECO #13132
7
PCMCIA Flash Memory Card
FLG Series
PC Card Products
150ns
200ns
SYMBOL
(PCMCIA)
Parameter
Min
Max
Min
Max
Unit
tCW
Write Cycle Time
150
200
ns
tw(WE)
Write Pulse Width
80
120
ns
tsu(A)
Address Setup Time
20
ns
tsu(A-WEH)
Address Setup Time for WE#
100
ns
tsu(CE-
WEH)
Card Enable Setup Time for WE#
100
ns
tsu(D-WEH)
Data Setup Time for WE#
50
ns
th(D)
Data Hold Time
20
ns
trec(WE)
Write Recover Time
20
ns
tdis(WE)
Output Disable Time from WE#
60
ns
tdis(OE)
Output Disable Time from OE#
60
ns
ten(WE)
Output Enable Time from WE#
55
ns
ten(OE)
Output Enable Time from OE#
55
ns
tsu(OE-WE)
Output Enable Setup from WE#
10
ns
th(OE-WE)
Output Enable Hold from WE#
10
ns
tsu(CE)
Card Enable Setup Time from OE#
0
ns
th(CE)
Card Enable Hold Time
20
ns
Note: AC timing diagrams and characteristics are guaranteed to meet or exceed PCMCIA 2.1 specifications.
Write Timing Diagram
Write Timing Parameters
th ( O E - W E )
NO T E 1
/C E 1 , /C E 2
NO T E 1
ts u ( C E - W E H )
tc ( W )
A [2 5 ::0 ], /R E G
tw ( W E )
td is ( W E )
th ( D )
D [ 15 : :0] ( D in )
DA T A I N P U T
ts u ( A )
ts u ( A - W E H )
/O E
ts u ( C E )
ts u ( D - W E H )
tr e c ( W E )
th ( C E )
ts u ( O E - W E )
td is ( O E )
D [ 15::0 ] ( D out )
te n ( O E )
te n ( W E )
NO T E 2
/W E
Notes:
1. Signal may be high or low in this area.
2. When the data I/O pins are in the output state, no signals shall be applied to the
data pins (D15 - D0) by the host system.
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