參數(shù)資料
型號(hào)： 7P1G0ATA2514C25
英文描述： Flash Memory Card(1024M位閃速存儲(chǔ)器卡)
中文描述： 閃存卡（1024M位閃速存儲(chǔ)器卡）
文件頁(yè)數(shù)： 36/62頁(yè)
文件大小： 626K
代理商： 7P1G0ATA2514C25
7PxxxATA25xxC25
June 2000 Rev. 1 – ECO #12936
36
White Electronic Designs Corporation
(508) 366-5151
12. Device control register:
This register is a write only register, and it is used for controlling the card
interrupt request and issuing an ATA soft reset to the card.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
×
×
×
×
1
SRST
nIEN
0
bit
Name
Function
7 to 4
×
don't care
3
1
This bit is set to "1".
2
SRST (Software ReSeT)
This bit is set to "1" in order to force the card to perform Task File
Reset operation. This does not change the Card Configuration
registers as a Hardware Reset does. The card remains in Reset
until this bit is reset to "0".
1
nIEN (Interrupt ENable)
This bit is used for enabling -IREQ. When this bit is set to "0", -IREQ
is enabled. When this bit is set to "1", -IREQ is disabled.
0
0
This bit is set to "0".
13. Drive Address register:
This register is a read only register, and it is used for confirming the drive
status. This register provides for compatibility with the AT disk drive interface. It is recommended that
this register not be mapped into the host’s I/O space because of potential conflicts on bit7.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
×
nWTG
nHS3
nHS2
nHS1
nHS0
nDS1
nDS0
bit
Name
Function
7
×
This bit is unknown
6
nWTG (WriTing Gate)
This bit is unknown
5 to 2 nHS3-0 (Head Select3-0)
These bits are the negative value of Head Select bits (bit 3 to 0) in
theDrive/Head register.
1
nDS1 (Idrive Select1)
This bit is unknown
0
nDS0 (Idrive Select0)
This bit is unknown
ATA Command Specifications
This table summarizes the ATA command set with the paragraphs. The following shows the support
commands and command codes which are written in the command registers.
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