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參數(shù)資料
| 型號： | 7P128FLF1400C25 |
| 英文描述： | Peripheral Miscellaneous |
| 中文描述： | 周邊雜項 |
| 文件頁數(shù)： | 13/17頁 |
| 文件大?。?/td> | 202K |
| 代理商： | 7P128FLF1400C25 |
November 2000 Rev. 3 - ECO #13392
5
PCMCIA Flash Memory Card
FLF10 Series
PC Card Products
Card Interface
The FLF10 series flash card complies with PC Card standard (PCMCIA, March 1997). While maintaining
PCMCIA compatibility, the FLF10 series card has integrated special features to extend functionality.
The card has built-in 2 control registers:
- Configuration Option Register (COR)
Address = 4000
h
- Configuration and Status Register (CSR)
Address = 4002
h
COR register: provides a soft reset function (bit D7) and additional page bits (bits D0 and D1) to extend
card capacity beyond 64MB.
SReset
As defined by PCMCIA, setting the SReset bit to 1, places the card in the reset state. During this state
all memory devices are placed in power down mode, minimizing power consumption. Returning this bit
to 0 leaves the reset cycle and places the card in the same condition as following a power up or hardware
reset. This bit must be cleared to 0, to access any device on the card.
Complete soft reset cycle must consist of a 2 step write sequence to the SReset bit:
1. Initialization: write 1 to SReset
- reset cycle begin
- memory devices enters Power-Down mode aborting all operations and clearing all registers.
2. Write 0 to SReset
- Reset cycle ends
- memory devices and registers enter power on default state
The card can also be placed in Power Down mode by activating the Reset signal (pin58) or by
controlling the bit D2 (PwrDwn) in the CSR register.
LevlRequest
Not supported
Configuration Index
Configuration Index bits (D0 - D5) are defined to provide address extension bits -page address, to extend
card capacity beyond 64MB.
Only bits D0 and D1 are supported:
- D1D0 set to 00
bin (0H) selects
page 0
- D1D0 set to 01
bin (1H) selects:
page 1
- D1D0 set to10
bin (2H) selects: page 2
- D1D0 set to11
bin (3H) selects: page 3 (No Memory Access)
D1D0 is set to the value of 00
bin (0H) during any reset cycle (Power on Reset, Hardware
Reset, and SReset). Attempting to access page 3 will not result in the writing or reading of
data.
CSR register: provides a power control of the memory array. Only bit D2 is supported; all other bits are
“don’t care”
PwrDwn
Writing 1 to PwrDwn bit (D2) forces each memory device on the card into a reset/power down mode by
asserting all the devices RP# pins. Writing 0 to the bit returns the array to stand by mode.
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