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參數(shù)資料
| 型號： | 7P032ATA2003C25 |
| 英文描述： | Flash Memory Card(32M位閃速存儲器卡) |
| 中文描述： | 閃存卡（32兆位閃速存儲器卡） |
| 文件頁數(shù)： | 6/66頁 |
| 文件大?。?/td> | 585K |
| 代理商： | 7P032ATA2003C25 |
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7PxxxATA20xxC25
June 2000 Rev. 5 – ECO #12935
6
White Electronic Designs Corporation
(508) 366-5151
Battery voltage detection, Digital audio output, Disk active/slave present (BVD2, -SPKR, -DASP:
input/output):
In memory card mode, BVD2 outputs the battery voltage status in the card. This card has
no battery, so this output is high level constantly. In the I/O card mode, -SPKR is held High because this
card does not have digital audio output. In True IDE Mode -DASP is the Disk Active/Slave Present signal
in the Master/Slave handshake protocol.
Reset (RESET, -RESET: input):
By assertion of the RESET signal, all registers of this card are cleared
and the RDY/-BSY signal turns to high level. In True IDE Mode -RESET is the active low hardware reset
from the host.
Wait (-WAIT, IORDY: output):
This signal outputs low level for the purpose of delaying memory access
cycle or I/O access cycle. In True IDE Mode this output signal may be used as IORDY. As for this
controller, this output is high impedance state constantly.
Input acknowledge (-INPACK: output):
This signal is not used in the memory card mode. This signal
is asserted by this card when the card is selected and responding to an I/O read cycle at the address that is
on the address bus. This signal is used for the input data buffer control. In True IDE Mode this output
signal is not used and should be kept open at the host side.
Battery voltage detection, Status change, Pass diagnostic (BVD1, -STSCHG, -PDIAG: input/output):
In the memory card mode, BVD1 outputs the battery voltage status in the card. This card has no battery, so
this output is high level constantly. In the I/O card mode, -STSCHG is used for changing the status of the
Configuration status register in the Attribute area, while the card is set I/O card interface. In True IDE
Mode, -PDIAG is the Pass Diagnostic signal in the Master/Slave handshake protocol.
V
CC
voltage sense (-VS1, -VS2: output):
These signals are intended to notify the socket of the PC Card's
CIS V
CC
requirement. -VS1 is held low and -VS2 is nonconnected in this card.
Card select (-CSEL: input):
This signal is not used in the memory card mode and I/O card mode. This
internally pulled up signal is used to configure this device as a Master or a Slave when configured in the
True IDE Mode. When this pin is grounded, this device is configured as a Master. When the pin is open,
this device is configured as a Slave.
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