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參數(shù)資料
| 型號： | 7P0160500I15 |
| 元件分類： | EEPROM |
| 英文描述： | EEPROM |
| 中文描述： | EEPROM的 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 111K |
| 代理商： | 7P0160500I15 |
August 2000 Rev. 3 - ECO #13135
3
PCMCIA Flash Memory Card
FVB Series
PC Card Products
Symbol
Type
Name and Function
A0 - A25
INPUT
ADDRESS INPUTS: A0 through A25 enable direct addressing of
up to 64MB of memory on the card. Signal A0 is not decoded since
the card is x16 only. The memory will wrap at the card density
boundary. The system should not try to access memory beyond the
card density. The upper addresses are not connected.
DQ0 - DQ15
INPUT/OUTP
UT
DATA INPUT/OUTPUT: DQ0 THROUGH DQ15 constitute the
bi-directional databus. DQ0 - DQ7 constitute the lower (even) byte
and DQ8 - DQ15 the upper (odd) byte. DQ15 is the MSB.
CE1#, CE2#
INPUT
CARD ENABLE 1 AND 2: CE1# enables even byte accesses, CE2#
enables odd byte accesses. Odd byte (DQ8 - DQ15) can not be
accessed on DQ0 - DQ7.
OE#
INPUT
OUTPUT ENABLE: Active low signal enabling read data from the
memory card.
WE#
INPUT
WRITE ENABLE: Active low signal gating write data to the
memory card.
RDY/BSY#
OUTPUT
READY/BUSY OUTPUT: Indicates status of internally timed erase
or program algorithms. A high output indicates that the card is ready
to accept accesses. Open Drain output, pull-up resistor is required.
CD1#, CD2#
OUTPUT
CARD DETECT 1 and 2: Provide card insertion detection. These
signals are connected to ground internally on the memory card. The
host socket interface circuitry shall supply 10K-ohm or larger pull-up
resistors on these signal pins.
WP
OUTPUT
WRITE PROTECT: This signal is pulled low internally. This
signifies write protect = "off " for all cases.
VPP1, VPP2
N.C.
PROGRAM/ERASE POWER SUPPLY: Not connected for 5V
only card.
VCC
CARD POWER SUPPLY: 5.0V for all internal circuitry.
GND
GROUND: for all internal circuitry.
REG#
INPUT
ATTRIBUTE MEMORY SELECT : only used with cards built
with optional attribute memory.
RST
INPUT
RESET: Active high signal for placing card in Power-on default
state. Reset can be used as a Power-Down signal for the memory
array.
WAIT#
OUTPUT
WAIT: This signal is pulled high internally for compatibility. No
wait states are generated.
BVD1, BVD2
OUTPUT
BATTERY VOLTAGE DETECT: These signals are pulled high to
maintain SRAM card compatibility.
VS1, VS2
OUTPUT
VOLTAGE SENSE: Notifies the host socket of the card's VCC
requirements. VS1 and VS2 are open to indicate a 5V, 16 bit card
has been inserted.
RFU
RESERVED FOR FUTURE USE
N.C.
NO INTERNAL CONNECTION TO CARD: pin may be driven
or left floating
Card Signal Description
READ function
Common Memory
Attribute Memory
Function Mode
/CE2
/CE1
/OE
/WE
/REG
D15-D8
D7-D0
/REG
D15-D8
D7-D0
Standby Mode
HH
X
High-Z
X
High-Z
Low Byte Access
HL
L
H
High-Z
Even-Byte
L
High-Z
Even-Byte
Word Access (16 bits)
LLL
H
Odd-Byte Even-Byte
L
Not Valid
Even-Byte
Odd-Byte Only Access
LH
H
Odd-Byte
High-Z
L
Not Valid
High-Z
WRITE function
Standby Mode
HH
X
XX
X
XX
Low Byte Access
HL
H
XEven-Byte
L
XEven-Byte
Word Access (16 bits)
LL
H
L
H
Odd-Byte Even-Byte
L
XEven-Byte
Odd-Byte Only Access
LH
H
L
H
Odd-Byte
X
L
XX
Functional Truth Table
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