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參數(shù)資料
| 型號： | 7LVC574APWDH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger 3-State |
| 中文描述： | LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 99K |
| 代理商： | 7LVC574APWDH |
Philips Semiconductors
Product specification
74LVC574A
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
2
1998 Jul 29
853-1863 19804
FEATURES
5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
Supply voltage range of 2.7V to 3.6V
Complies with JEDEC standard no. 8-1A
Inputs accept voltages up to 5.5V
CMOS low power consumption
Direct interface with TTL levels
High impedance when V
CC
= 0V
8-bit positive edge-triggered register
Independent register and 3-State buffer operation
Flow-through pin-out architecture
DESCRIPTION
The 74LVC574A is a high-performance, low-power, low-voltage,
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3V or 5V devices. In 3-State
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
The 74LVC574A is an octal D-type flip-flop featuring separate
D-type inputs for each flip-flop and 3-State outputs for bus-oriented
applications. A clock (CP) and an output enable (OE) input are
common to all flip-flops.
The eight flip-flops will store the state of their individual D-inputs
that meet the setup and hold times requirements on the
LOW-to-HIGH CP transition.
When OE is LOW, the contents of the eight flip-flops is available at
the outputs. When OE is HIGH, the outputs go to the high
impedance OFF-state. Operation of the OE input does not affect the
state of the flip-flops.
The ’574A’ is functionally identical to the ’374A’, but the ’374A’ has a
different pin arrangement.
QUICK REFERENCE DATA
GND = 0V; T
amb
=25
°
C; t
r
= t
f
SYMBOL
2.5ns
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
CP to Q
n
maximum clock frequency
C
L
= 50pF
V
CC
= 3.3V
4.8
ns
f
max
C
I
150
MHz
Input capacitance
5.0
pF
C
PD
Power dissipation capacitance per
flip-flop
Notes 1 and 2
20
pF
NOTE:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in W):
P
D
= C
PD
x V
CC2
x f
i
+ (C
L
x V
CC2
x f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
x V
CC2
x f
o
) = sum of outputs.
2. The condition is V
I
= GND to V
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE
RANGE
OUTSIDE
NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
20-Pin Plastic Shrink Small Outline (SO)
–40
°
C to +85
°
C
74LVC574A D
74LVC574A D
SOT163-1
20-Pin Plastic Shrink Small Outline (SSOP) Type II
–40
°
C to +85
°
C
74LVC574A DB
74LVC574A DB
SOT339-1
20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I
–40
°
C to +85
°
C
74LVC574A PW
7LVC574APW DH
SOT360-1
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PDF描述 |
|---|---|
| 7LVC623APWDH | Octal transceiver with dual enable 3-State |
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| 7LVC827APWDH | 10-bit buffer/line driver with 5-volt tolerant inputs/outputs 3-State |
| 7LVC841APWDH | 10-bit transparent latch with 5-volt tolerant inputs/outputs 3-State |
| 7LVT2241PWDH | 3.3V Octal buffer/line driver with 30ohm series termination resistors; 3-State |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 7LVC623APWDH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Octal transceiver with dual enable 3-State |
| 7LVC646APWDH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Octal bus transceiver/register 3-State |
| 7LVC827APWDH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:10-bit buffer/line driver with 5-volt tolerant inputs/outputs 3-State |
| 7LVC841APWDH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:10-bit transparent latch with 5-volt tolerant inputs/outputs 3-State |
| 7LVT2241PWDH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3.3V Octal buffer/line driver with 30ohm series termination resistors; 3-State |
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