參數(shù)資料
型號(hào): 7LVC543APWDH
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: Octal D-type registered transceiver 3-State
中文描述: LVC/LCX/Z SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24
文件頁(yè)數(shù): 7/12頁(yè)
文件大?。?/td> 104K
代理商: 7LVC543APWDH
Philips Semiconductors
Product specification
74LVC543A
Octal D-type registered transceiver (3-State)
1998 Jul 31
7
AC WAVEFORMS
V
M
= 1.5V at V
V
OL
and V
are the typical output voltage drop that occur with the output load.
V
X
= V
OL
+ 0.3V at V
CC
2.7V; V
X
= V
OL
+ 0.1 V
CC
at V
CC
V
Y
= V
OH
–0.3V at V
CC
2.7V; V
Y
= V
OH
– 0.1 V
CC
at V
CC
2.7V; V
= 0.5 V
at V
2.7V.
2.7V
2.7V
SY00041
INPUT
V
M
t
PHL
t
PLH
V
OL
V
I
V
M
GND
V
OH
OUTPUT
Waveform 1. Input (A
n
, B
n
) to output (B
n
, A
n
) propagation
delays.
t
w
t
PHL
t
PLH
LE
XX
INPUT
A
, B
n
OUTPUT
V
M
V
M
V
M
V
M
V
M
V
I
GND
V
OH
V
OL
SA00408
Waveform 2. Latch enable input (LE
XX
) pulse width and the
latch enable input to output (A
n
, B
n
) propagation delays.
t
PLZ
t
PZL
V
I
OE
, E
XX
INPUT
GND
V
CC
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
OL
V
OH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
outputs
enabled
outputs
enabled
outputs
disabled
t
PHZ
V
M
V
M
V
M
t
PZH
V
X
V
Y
SW00210
Waveform 3. 3-State enable and disable times
ééé
ééé
éééééééé
éééééééé
th
th
A
, B
n
INPUT
V
M
LE
, E
XX
INPUT
GND
t
SU
NOTE:
The shaded areas indicate when the input is permitted to change
for predictable output performance.
t
SU
V
I
GND
V
I
SW00211
Waveform 4. Data setup and hold times for the (A
n
, B
n
) input
to the LE
XX
and E
XX
inputs.
TEST CIRCUIT
PULSE
GENERATOR
R
T
V
IN
D.U.T.
V
OUT
C
L
V
CC
R
L
=500
SWITCH POSITION
TEST
t
PLH
/t
PHL
t
PLZ
/t
PZL
t
PHZ
/t
PZH
SWITCH
Open
2
V
CC
GND
Test Circuit for 3-State Outputs
Open
GND
S
1
2
V
CC
DEFINITIONS
R
L
= Load resistor
C
L
= Load capacitance includes jig and probe capacitance
R
T
=Termination resistance should be equal to Z
OUT
of pulse generators.
V
CC
2.7V
2.7 – 3.6V
V
IN
V
CC
2.7V
SW00047
R
L
=500
Waveform 5. Load circuitry for switching times.
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