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參數(shù)資料
| 型號： | 7B991RPFI |
| 廠商： | MAXWELL TECHNOLOGIES |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | Programmable Skew Clock Buffer (PSCB) |
| 中文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), DFP32 |
| 封裝： | RAD PAK, DFP-16 |
| 文件頁數(shù)： | 12/17頁 |
| 文件大小： | 253K |
| 代理商： | 7B991RPFI |
M
12
All data sheets are subject to change without notice
2002 Maxwell Technologies.
All rights reserved.
Programmable Skew Clock Buffer (PSCB)
7B991
09.23.02 Rev 4
Clock skews can be advanced by ± 6 time units (t
U
) when using an output selected for zero skew as the feedback. A
wider range of delays is possible if the output connected to FB is also skewed. Since
“
Zero Skew
”
, +t
U
and -t
U
are
defined relative to output groups, and since the PLL aligns the rising edges of REF and FB, it is possible to create
wider output skews by proper selection of the xFn inputs. For example, a +10 t
U
between REG and 3Qx can be
achieved by connecting 1Q0 to FB and setting 1F0 = 1F1 = GND, 3F0 = MID, and 3F1 = HIGH (Since FB aligns at -4
t
U
and 3Qx skews to +6 t
U
, a total of +10 t
U
skew is realized.). Many other configurations can be realized by skewing
both the output used as the FB input and skewing the other outputs.
F
IGURE
7. I
NVERTED
O
UTPUT
C
ONNECTIONS
Figure shows an example of the invert function of the PSCB. In this example the 4Q0 output used as the FB input is
programmed for invert (4F0 = 4F1 = HIGH) while the other three pairs of outputs are programmed for zero skew
When 4F0 and 4F1 are tied high, 4Q0 and 4Q1 become inverted zero phase outputs. The PLL aligns the rising edge
of the FB input with the rising edge of the REF. This causes the 1Q, 2Q, and 3Q outputs to become the
“
inverted
”
out-
puts with respect to the REF input. By selecting which output connects to FB, it is possible to have 2 inverted and 6
non-inverted output or 6 inverted and 2 non-inverted outputs. The correct configuration would be determned by the
need for more (or fewer) inverted outputs. 1Q, 2Q, and 3Q outputs can also be skewed to compensate for varying
trace delays independent of inversion on 4Q.
F
IGURE
8. F
REQUENCY
M
ULTIPLIER
WITH
S
KEW
C
ONNECTIONS
Figure illustrates the PSCB configured as a clock multiplier. The 3Q0 output is programmed to divide by four and is
fed back to FB. This causes the PLL to increase its frequency until the 3Q0 and 3Q1 outputs are locked at 20 MHz
while the 1Qx and 2Qx outputs run at 80 MHz. The 4Q0 and 4Q1 outputs are programmed to divide by two, which
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