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參數(shù)資料
| 型號： | 79RC32V364100DAI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISController Embedded 32-bit Microprocessor, based on RISCore32300 |
| 中文描述： | 32-BIT, 100 MHz, RISC PROCESSOR, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144 |
| 文件頁數(shù)： | 3/21頁 |
| 文件大?。?/td> | 370K |
| 代理商： | 79RC32V364100DAI |
3 of 21
June 20, 2000
79RC32364
*Notice: The information in this document is subject to change without notice
Two atomic operations—multiply-add (MAD) and multiply-subtract
(MSUB)—are used to perform the multiply-accumulate and multiply-
subtract operations. The MAD instruction multiplies two numbers and
then adds the product to the current contents of the HI and LO registers.
Similarly, the MSUB instruction multiplies two operands and then
subtracts the product from the HI and LO registers.
The MAD and MSUB operations are used in numerous DSP algo-
rithms and allow the RC32364 to cost reduce systems requiring a mix of
DSP and control functions.
Finally, for these operations, aggressive implementation techniques
feature low latency along with pipelining to allow the issuance of new
operations before a previous operation has been completed. The
RC32364 also performs automatic operand size detection and imple-
ments hardware interlocks to prevent overrun, achieving high-perfor-
mance with simple programming.
System Control Coprocessor (CP0)
In the MIPS architecture, the system control co-processor is respon-
sible for the virtual-to-physical address translation and cache protocols,
the exception control system, and the processor’s diagnostics capability.
Also, the system control co-processor (and thus the kernel software) is
implementation dependent.
Although the RISCore32300 implements a 32-bit ISA, the Memory
Management Unit (MMU) that the RC32364 incorporates is modeled
after the MMU found in the 64-bit RC5000 family and offers variable
page size, enhanced cache write algorithm support, mapping of a larger
portion of the virtual address space and a variable number of locked
entries, relative to the traditional 32-bit R3000 style MMU.
The RC32364’s translation lookaside buffer (TLB) contains 16
entries, mapping a total of 32 pages or as much as 512 MB of memory
at a time.
The exception model that is implemented in the RC32364 is also
consistent with that of the RC5000 family, including the treatment of
kernel mode and exception processing.
The RC32364 incorporates all
system control co-processor (CP0
)
registers on-chip. These registers provide the path through which the
virtual memory system’s address translation is controlled, exceptions
are handled, and operating modes are selected (for example, kernel vs.
user mode, interrupts enabled or disabled, and cache features).
In addition, the RC32364 includes registers to implement a real-time
cycle counting facility, which aids in cache diagnostic testing, assists in
data error detection, and facilitates software debug. Alternatively, this
timer can be used as the operating system reference timer and can
signal a periodic interrupt.
Operation Modes
The RC32364 supports two modes of operation: user mode and
kernel mode. User mode is most often used for applications programs,
and the kernel mode is typically used for handling exceptions and oper-
ating system kernel functions, including CP0 management and I/O
device access.
The processor enters kernel mode at reset and when an exception is
recognized. While in kernel mode, software has access to the entire
address space as well as all of the CP0 registers. User mode accesses
are limited to a subset of the virtual address space and can be inhibited
from accessing CP0 functions.
Virtual-to-Physical Address Mapping
The RC32364’s 4GB virtual address space is divided into addresses
that are accessible in either kernel or user mode (kuseg) and those that
are accessible only in kernel mode (kseg2:0).
Bits in a status register determine which virtual addressing mode will
be used. While in user mode, the RC32364 provides a single, uniform
2GB virtual address space for the user’s program. While operating in
kernel mode, four distinct virtual address spaces, totalling 4GB, are
simultaneously available and are differentiated by the high-order bits of
the virtual address.
The RC32364 reserves a small portion of the kernel address space
for on-chip resources. These resources include those used by the
Enhanced JTAG unit as well as registers used to configure the system
bus interface.
For fast virtual-to-physical address decoding, the RC32364 uses a
fully associative
translation lookaside buffer (TLB)
that maps 32
virtual pages to their corresponding physical addresses. The TLB is
organized as 16 pairs of even/odd entries mapping pages of sizes that
vary from 4kBytes to 16 MBytes into the 4GB physical address space.
To assist in controlling both the amount of mapped space and the
replacement characteristics of various memory regions, the RC32364
provides two mechanisms. First, the page size can be configured, on a
per entry basis, to map a page size of 4kB to 16MB (in multiples of 4). A
CP0 register is loaded with the mapping page size which is then entered
into the TLB when a new entry is written. Thus, operating systems can
provide special purpose maps; for example, a typical frame buffer can
be memory mapped with only one TLB entry.
The second mechanism controls the replacement algorithm, when a
TLB miss occurs. To select a TLB entry to be written with a new
mapping, the RC32364 provides a random replacement algorithm;
however, the processor provides a mechanism whereby a system
specific number of mappings can be locked into the TLB and thus avoid
being randomly replaced. This facilitates the design of real-time
systems, by allowing deterministic access to critical software.
The RC32364’s TLB also contains information to control the cache
coherency protocol for each page. Specifically, each page has attribute
bits to determine whether the coherency algorithm is uncached, non-
coherent write-back, or non-coherent write-through no write-allocate.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
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| 79RC32V364133DA | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:RISController Embedded 32-bit Microprocessor, based on RISCore32300 |
| 79RC32V364-133DA | 制造商:Integrated Device Technology Inc 功能描述:MPU RC32300 RISC 32-Bit 133MHz 3.3V 144-Pin TQFP |
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| 79RC32V364133DAI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:RISController Embedded 32-bit Microprocessor, based on RISCore32300 |
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