參數(shù)資料
型號(hào): 79RC32V364100DA
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 微控制器/微處理器
英文描述: RISController Embedded 32-bit Microprocessor, based on RISCore32300
中文描述: 32-BIT, 100 MHz, RISC PROCESSOR, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144
文件頁(yè)數(shù): 2/21頁(yè)
文件大小: 370K
代理商: 79RC32V364100DA
2 of 21
June 20, 2000
79RC32364
Device
Targeted to a variety of performance-hungry, cost-sensitive
embedded applications, the RC32364 is a new low-powered, low-cost
member of the Integrated Device Technology, Inc. (IDT) RISController
Series of Embedded Microprocessors.
*Notice: The information in this document is subject to change without notice
Ov
erview
The RC32364 brings 64-bit performance levels to lower cost
systems. High performance is achieved through the use of advanced
techniques such as large on-chip two-way set-associative caches, a
streamlined high-speed pipeline, high-bandwidth, and facilities such as
early restart for data cache misses. Also, through IDT proprietary
enhancements to the base MIPS architecture, the processor’s perfor-
mance, in particular applications, is further extended.
The RC32364 is the first member of a new processor family that uses
IDT’s proprietary RISCore32300 CPU core. The RISCore32300 core
continues IDT’s tradition of high-performance through high-speed pipe-
lines, high-bandwidth caches, and architectural extensions that serve
the needs of specific markets; yet the RC32364 provides these capabili-
ties in a low-cost, high-speed 32-bit enhanced MIPS architecture core,
enabling a new level of price performance.
Around the RISCore32300, the RC32364 integrates a fully RC5000
compatible memory management unit (MMU), substantial amounts of
efficient cache memory, an enhanced debug capability, digital signal
processing (DSP) extensions, and a low-cost system interface. The
resulting device is well suited to the needs of mid-range communications
equipment, xDSL equipment, and consumer devices.
Also, being upwardly software compatible with the RC3000 family,
the RC32364 will serve in many of the same applications as well as
support applications that require integer DSP functions.
Device Performance
RC32364 is rated at 175 dhrystone MIPS at 133MHz. The internal
cache bandwidth is over 1.2 GB/sec, with external bus bandwidth of
260MB/sec. Computational performance is further enhanced by the
device’s DSP capability, which supports 66 Million multiply-accummulate
(MAC) operations per second at 133MHz.
The RISCore32300
uses a 5-stage pipeline, similar to the
RISCore3000 and the RISCore4000 processor families. The simplicity
of the pipeline enables the processor to achieve high frequency while
minimizing device complexity, reducing both cost and power consump-
tion. Because this pipeline is not sensitive to the data conflicts that slow-
down super-scalar machines, an added benefit to this pipeline approach
is that sustained actual performance is much closer to the theoretical
maximum performance.
The
RISCore32300 integer execution unit
implements the MIPS 32
ISA. The RISCore32300 thus implements a load/store architecture with
single-cycle ALU operations (logical, shift, add, subtract) and an autono-
mous multiply/divide unit. The 32-bit register resources include 32
general-purpose orthogonal integer registers, the HI/LO result register
for the integer multiply/divide unit, and the program counter.
RISCore32300 CPU core features include:
N
MIPS IV prefetch operations, with various innovative hint
subfields
N
MIPS IV compatible conditional move instructions
N
MAD, MUL and MSUB instructions added to the integer multiply
units
N
Two new instructions: Count Leading Ones (CLO) and Counts
Leading Zeros (CLZ)
These integer unit enhancements combine to make the CPU well
suited to applications that require high bandwidth, rapid computation,
and/or DSP capability.
The RISCore32300 register file
has 32 general-purpose 32-bit
registers that are used for scalar integer operations and address calcu-
lation. The register file consists of two read ports and two write ports
and is fully bypassed to minimize operation latency in the pipeline.
The RISCore32300 arithmetic logic unit
(ALU) consists of the
integer adder and logic unit. The adder performs address calculations in
addition to arithmetic operations; the logic unit performs all of the logic
and shift operations. Each unit is highly optimized and can perform an
operation in a single pipeline cycle.
The RC32364 uses a dedicated
integer multiply/divide unit
, opti-
mized for high-speed multiply and multiply-accumulate operations.
Table 1 lists the repeat rate (peak issue rate of cycles until the operation
can be reissued), latency (number of cycles until a result is available),
and number of processor stalls (number of cycles that the CPU will
always delay the pipeline) required for these operations. Each rate listed
is expressed in terms of pipeline clocks.
The original MIPS architecture defines that the results of a multiply
or divide operation are placed in the HI and LO registers. Using the
move-from-HI (MFHI) and move-from-LO (MFLO) instructions, these
values can then be transferred to the general purpose register file.
As an enhancement to the original MIPS ISA, the RC32364 imple-
ments an additional multiply instruction, MUL, which specifies that
multiply results bypass the LO register and be placed immediately into
the primary register file. By avoiding the explicit MFLO instruction,
required when using LO, and by supporting multiple destination regis-
ters, the throughput of multiply-intensive operations is increased.
Opcode
Operand
Size
Latency
Repeat
Stall
MULT/U,
MAD/U
MSUB/U
16 bit
3
2
0
32 bit
4
3
0
MUL
16 bit
3
2
1
32 bit
4
3
2
DIV, DIVU
any
36
36
0
Table 1 RISCore32300 Integer Multiply/Divide Unit Operation Frequency
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參數(shù)描述
79RC32V364-100DA8 制造商:Integrated Device Technology Inc 功能描述:MPU RC32300 RISC 32BIT 100MHZ 3.3V 144TQFP - Tape and Reel
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