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IDT EJTAG System
EJTAG Processor Core Extensions
79RC32438 User Reference Manual
20 - 28
November 4, 2002
Notes
DDBSImpr
19
Indicates that a Debug Data Break Store Imprecise exception
due to a store was the cause of the debug exception, or that an
imprecise data hardware break due to a store was indicated
after another debug exception occurred. Cleared on exception
in Debug Mode.
0: No match of an imprecise data hardware breakpoint on
store
1: Match of imprecise data hardware breakpoint on store
R
0
Note:
This
value is
always 0.
DDBLImpr
18
Indicates that a Debug Data Break Load Imprecise exception
due to a load was the cause of the debug exception, or that an
imprecise data hardware break due to a load was indicated
after another debug exception occurred. Cleared on exception
in Debug Mode.
0: No match of an imprecise data hardware breakpoint on
load
1: Match of imprecise data hardware breakpoint on load
R
0
Note:
This
value is
always 0.
EJTAGver
17:15
Provides the EJTAG version.
0: Version 1 and 2.0
1: Version 2.5
2-7: Reserved
R
1
Note:
This
value is
always 1.
DExcCode
14:10
Indicates the cause of the latest exception in Debug Mode.
The field is encoded as the ExcCode field in the Cause register
for those exceptions that can occur in Debug Mode (the encod-
ing is shown in MIPS32 and MIPS64 specifications), with addi-
tion of code 30 with the mnemonic CacheErr for cache errors.
R
Undefined
NoSSt
9
Indicates whether the single-step feature controllable by the
SSt bit is available in this implementation:
0: Single-step feature available
1: No single-step feature available
A minimum number of hardware instruction breakpoints must
be available if no single-step feature is implemented in hard-
ware. Refer to section “Number of Instruction Breakpoints
Without Single Stepping” on page 20-52 for more information.
R
0
Note:
This
value is
always 0.
SSt
8
Controls whether single-step feature is enabled:
0: No enable of single-step feature
1: Single-step feature enabled
R/W
0
0
7:6
Must be written as zeros; return zeros on reads.
0
0
DINT
5
Indicates that a Debug Interrupt exception occurred. Cleared
on exception in Debug Mode.
0: No Debug Interrupt exception
1: Debug Interrupt exception
R
Undefined
DIB
4
Indicates that a Debug Instruction Break exception occurred.
Cleared on exception in Debug Mode.
0: No Debug Instruction Break exception
1: Debug Instruction Break exception
R
Undefined
Fields
Name Bits
Description
Read/
Write
Reset
State
Table 20.16 Debug Register Field Descriptions (Part 3 of 4)