參數(shù)資料
型號: 79RC32K438-200BB
廠商: Integrated Device Technology, Inc.
英文描述: IDTTM InterpriseTM Integrated Communications Processor
中文描述: IDTTM InterpriseTM集成通信處理器
文件頁數(shù): 16/59頁
文件大小: 644K
代理商: 79RC32K438-200BB
16 of 59
May 25, 2004
IDT 79RC32438
MDATA[7]
Boot Device Width
. This field specifies the width of the boot device (i.e., Device 0).
0x0 - 8-bit boot device width
0x1 - 16-bit boot device width
MDATA[8]
Reset Mode
. This bit specifies the length of time the RSTN signal is driven.
0x0 - Normal reset: RSTN driven for minimum of 4096 clock cycles
0x1 - reserved
MDATA[11:9]
PCI Mode
. This bit controls the operating mode of the PCI bus interface. The initial
value of the EN bit in the PCIC register is determined by the PCI mode.
0x0 - Disabled (EN initial value is zero)
0x1 - PCI satellite mode with PCI target not ready (EN initial value is one)
0x2 - PCI satellite mode with suspended CPU execution (EN initial value is one)
0x3 - PCI host mode with external arbiter (EN initial value is zero)
0x4 - PCI host mode with internal arbiter using fixed priority arbitration algorithm
(EN initial value is zero)
0x5 - PCI host mode with internal arbiter using round robin arbitration algorithm
(EN initial value is zero)
0x6 -
reserved
0x7 -
reserved
MDATA[12]
Disable Watchdog Timer
. When this bit is set, the watchdog timer is disabled follow-
ing a cold reset.
0x0 - Watchdog timer enabled
0x1 - Watchdog timer disabled
MDATA[15:13]
Reserved
. These pins must be driven low during boot configuration.
Signal
Name/Description
Table 3 Boot Configuration Encoding (Part 2 of 2)
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