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參數(shù)資料
| 型號： | 79RC32H435-400BC |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | IDTTM InterpriseTM Integrated Communications Processor |
| 中文描述： | IDTTM InterpriseTM集成通信處理器 |
| 文件頁數(shù)： | 34/53頁 |
| 文件大?。?/td> | 444K |
| 代理商： | 79RC32H435-400BC |
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34 of 53
January 19, 2006
IDT 79RC32435
Using the EJ TAG Probe
In Figure 20, the pull-up resistors for JTAG_TDO and RST* the pull-down resistor for JTAG_TRST_N, and the series resistor for JTAG_TDO must
be adjusted to the specific design. However, the recommended pull-up/down resistor is 1.0 k
because a low value reduces crosstalk on the cable to
the connector, allowing higher JTAG_TCK frequencies. A typical value for the series resistor is 33
. Recommended resistor values have ± 5% toler-
ance.
If a probe is used, the pull-up resistor on JTAG_TDO must ensure that the JTAG_TDO level is high when no probe is connected and the
JTAG_TDO output is tri-stated. This requirement allows reliable connection of the probe if it is hooked-up when the power is already on (hot plug). The
pull-up resistor value of around 47 k
should be sufficient. Optional diodes to protect against overshoot and undershoot voltage can be added on the
signals of the chip with EJTAG.
If a probe is used, the RST*signal must have a pull-up resistor because it is controlled by an open-collector (OC) driver in the probe, and thus is
actively pulled low only. The pull-up resistor is responsible for the high value when not driven by the probe of 25pF. The input on the target system
reset circuit must be able to accept the rise time when the pull-up resistor charges the capacitance to a high logical level. Vcc I/O must connect to a
voltage reference that drops rapidly to below 0.5V when the target systemloses power, even with a capacitive load of 25pF. The probe can thus detect
the lost power condition.
For additional information on EJTAG, refer to Chapter 17 of the RC32435 User Reference Manual.
Phase-Locked Loop (PLL)
The phase-locked loop (PLL) multiplies the external oscillator input (pin CLK) according to the parameter provided by the boot configuration vector
to create the processor clock (PCLK). Inherently, PLL circuits are only capable of generating clock frequencies within a limted range.
PLL Filters
It is recommended that the systemdesigner provide a filter network of passive components for the PLL analog and digital power supplies.
The
PLL
circuit power and PLL circuit ground should be isolated frompower and ground with a filter circuit such as the one shown in Figure 21. Because the
optimumvalues for the filter components depend upon the application and the systemnoise environment, these values should be considered as
starting points for further experimentation within your specific application.
Figure 21 PLL Filter Circuit for Noisy Environments
10
μ
F
0.1
μ
F
100 pF
V
cc
V
ss
V
cc
PLL
V
ss
PLL
10 ohm
1
RC32435
V
cc
PLL
V
ss
PLL
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| 79RC32K438-200BBI | IDTTM InterpriseTM Integrated Communications Processor |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 79RC32H435-400BCG | 功能描述:處理器 - 專門應用 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| 79RC32H435-400BCI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDTTM InterpriseTM Integrated Communications Processor |
| 79RC32K438200BB | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDTTM InterpriseTM Integrated Communications Processor |
| 79RC32K438-200BB | 功能描述:處理器 - 專門應用 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| 79RC32K438-200BBG | 功能描述:處理器 - 專門應用 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
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