參數(shù)資料
型號(hào)： 79RC32H435-350BC
廠商： Integrated Device Technology, Inc.
英文描述： IDTTM InterpriseTM Integrated Communications Processor
中文描述： IDTTM InterpriseTM集成通信處理器
文件頁(yè)數(shù)： 4/53頁(yè)
文件大?。?/td> 444K
代理商： 79RC32H435-350BC
4 of 53
January 19, 2006
IDT 79RC32435
Pin Desc ription Table
The following table lists the functions of the pins provided on the RC32435. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero
(low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
S ignal
Type
Name/Desc ription
Memory and Peripheral Bus
BDIRN
O
External Buffer Direction.
Controls the direction of the external data bus buffer
for the memory and peripheral bus. If the RC32435 memory and peripheral bus
is connected to the A side of a transceiver, such as an IDT74FCT245, then this
pin may be directly connected to the direction control (e.g., BDIR) pin of the
transceiver.
BOEN
O
External Buffer Enable.
This signal provides an output enable control for an
external buffer on the memory and peripheral data bus.
WEN
O
Write Enables.
This signal is the memory and peripheral bus write enable sig-
nal.
CSN[3:0]
O
Chip Selects.
These signals are used to select an external device on the mem-
ory and peripheral bus.
MADDR[21:0]
O
Address Bus.
22-bit memory and peripheral bus address bus.
MADDR[25:22] are available as GPIO alternate functions.
MDATA[7:0]
I/O
Data Bus.
8-bit memory and peripheral data bus. During a cold reset, these pins
function as inputs that are used to load the boot configuration vector.
OEN
O
Output Enable.
This signal is asserted when data should be driven by an exter-
nal device on the memory and peripheral bus.
RWN
O
Read Write.
This signal indicates whether the transaction on the memory and
peripheral bus is a read transaction or a write transaction. A high level indicates
a read froman external device. A low level indicates a write to an external
device.
WAITACKN
I
Wait or Transfer Acknowledge.
When configured as wait, this signal is
asserted during a memory and peripheral bus transaction to extend the bus
cycle. When configured as a transfer acknowledge, this signal is asserted during
a transaction to signal the completion of the transaction.
DDR Bus
DDRADDR[13:0]
O
DDR Address Bus.
14-bit multiplexed DDR address bus. This bus is used to
transfer the addresses to the DDR devices.
DDRBA[1:0]
O
DDR Bank Address.
These signals are used to transfer the bank address to the
DDRs.
DDRCASN
O
DDR Column Address Strobe.
This signal is asserted during DDR transac-
tions.
DDRCKE
O
DDR Clock Enable.
The DDR clock enable signal is asserted during normal
DDR operation. This signal is negated following a cold reset or during a power
down operation.
DDRCKN
O
DDR Negative DDR clock.
This signal is the negative clock of the differential
DDR clock pair.
Table 1 Pin Description (Part 1 of 6)
相關(guān)PDF資料
PDF描述
79RC32H435-350BCI IDTTM InterpriseTM Integrated Communications Processor
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79RC32H435-350BCG 功能描述:處理器 - 專門應(yīng)用 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
79RC32H435-350BCGI 功能描述:處理器 - 專門應(yīng)用 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
79RC32H435-350BCI 制造商:Integrated Device Technology Inc 功能描述:MPU RC32435 RISC 32-Bit 350MHz 2.5V/3.3V 256-Pin CABGA 制造商:Integrated Device Technology Inc 功能描述:COMMUNICATIONS PROCESSOR 256CABGA - Bulk
79RC32H435-400BC 功能描述:處理器 - 專門應(yīng)用 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
79RC32H435-400BCG 功能描述:處理器 - 專門應(yīng)用 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
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