7 of 42
May 25, 2004
IDT 79RC32351
GPIOP[5]
I/O
Low Drive
with STI
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function: UART channel 0 data set ready, U0DSRN.
GPIOP[6]
I/O
Low Drive
with STI
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function: UART channel 0 request to send, U0RTSN.
GPIOP[7]
I/O
Low Drive
with STI
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function: UART channel 0 clear to send, U0CTSN.
GPIOP[8]
I/O
Low Drive
with STI
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
1st Alternate function: UART channel 1 serial output, U1SOUTP.
2nd Alternate function: Active DMA channel code, DMAP[3].
GPIOP[9]
I/O
Low Drive
with STI
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
1st Alternate function: UART channel 1 serial input, U1SINP.
2nd Alternate function: Active DMA channel code, DMAP[2].
GPIOP[10]
I/O
Low Drive
with STI
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
1st Alternate function: UART channel 1 data terminal ready, U1DTRN.
2nd Alternate function: ICE PC trace status, EJTAG_PCST[0].
GPIOP[11]
I/O
Low Drive
with STI
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
1st Alternate function: UART channel 1 data set ready, U1DSRN.
2nd Alternate function: ICE PC trace status, EJTAG_PCST[1].
GPIOP[12]
I/O
Low Drive
with STI
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
1st Alternate function: UART channel 1 request to send, U1RTSN.
2nd Alternate function: ICE PC trace status, EJTAG_PCST[2].
GPIOP[13]
I/O
Low Drive
with STI
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
1st Alternate function: UART channel 1 clear to send, U1CTSN.
2nd Alternate function: ICE PC trace clock, EJTAG_DCLK.
GPIOP[14]
I/O
Low Drive
with STI
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIOP[15]
I/O
Low Drive
with STI
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIOP[16]
I/O
High Drive
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function: Memory and peripheral bus chip select, CSN[4].
GPIOP[17]
I/O
High Drive
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function: Memory and peripheral bus chip select, CSN[5].
GPIOP[18]
I/O
Low Drive
with STI
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function: External DMA device request, DMAREQN.
GPIOP[19]
I/O
Low Drive
with STI
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function: External DMA device done, DMADONEN.
GPIOP[20]
I/O
Low Drive
with STI
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function: USB start of frame, USBSOF.
GPIOP[21]
I/O
Low Drive
with STI
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function: SDRAM clock enable CKENP.
GPIOP[22]
I/O
Low Drive
with STI
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function: ATM transmit PHY address, TXADDR[0].
GPIOP[23]
I/O
Low Drive
with STI
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
1st Alternate function: ATM transmit PHY address, TXADDR[1].
2nd Alternate function: Active DMA channel code, DMAP[0].
Name
Type I/O Type
Description
Table 1 Pin Descriptions (Part 3 of 7)