參數(shù)資料
型號(hào)： 79RC32334-133BBGI
廠商： Integrated Device Technology, Inc.
英文描述： IDT Interprise Integrated Communications Processor
中文描述： IDT的洽談會(huì)集成通信處理器
文件頁(yè)數(shù)： 11/30頁(yè)
文件大?。?/td> 467K
代理商： 79RC32334-133BBGI
11 of 30
August 31, 2004
IDT 79RC32334—Rev. Y
Mode Bit Settings to Configure Controller on Reset
The following table lists the mode bit settings to configure the controller on cold reset.
Debug Signals
debug_cpu_dma_n
I/O
Z
Low
Debug CPU versus DMA Negated
De-assertion high during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transac-
tion was generated from the CPU.
Assertion low during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction
was generated from DMA.
Alternate function: modebit[6].
debug_cpu_ack_n
I/O
Z
Low
Debug CPU Acknowledge Negated
Indicates either a data acknowledge to the CPU or DMA.
Alternate function: modebit[4].
debug_cpu_ads_n
I/O
Z
Low
Debug CPU Address/Data Strobe Negated
Assertion indicates that either a CPU or a DMA transaction is beginning and that the mem_data[31:4] bus
has the current block address.
Alternate function: modebit[5].
debug_cpu_i_d_n
I/O
Z
Low
Debug CPU Instruction versus Data Negated
Assertion during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction is a
CPU or DMA data transaction.
De-assertion during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction is a
CPU instruction transaction.
Alternate function: modebit[3].
Pin
Mode Bit
Description
Value
Mode Setting
ejtag_pcst[2:0]
2:0 MSB (2)
Clock Multiplier
MasterClock
is multiplied internally to gener-
ate PClock
0
Multiply by 2
1
Multiply by 3
2
Multiply by 4
3
Reserved
4
Reserved
5
Reserved
6
Reserved
7
Reserved
debug_cpu_i_d_n
3
EndBit
0
Little-endian ordering
1
Big-endian ordering
debug_cpu_ack_n
4
Reserved
0
debug_cpu_ads_n
5
Reserved
0
debug_cpu_dma_n
6
TmrIntEn
Enables/Disables the timer interrupt on Int*[5]
0
Enables timer interrupt
1
Disables timer interrupt
mem_addr[17]
7
Reserved for future use
1
Table 2 Boot-Mode Configuration Settings (Part 1 of 2)
Name
Type
Reset
State
Status
Drive
Strength
Capability
Description
Table 1 Pin Description (Part 7 of 7)
相關(guān)PDF資料
PDF描述
79RC32334-133BBI IDT Interprise Integrated Communications Processor
79RC32334-150BB IDT Interprise Integrated Communications Processor
79RC32351 IDT Interprise Integrated Communications Processor
79RC32351-100DH IDT Interprise Integrated Communications Processor
79RC32351-133DH IDT Interprise Integrated Communications Processor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
79RC32334-133BBI 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDT Interprise Integrated Communications Processor
79RC32334-150BB 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDT Interprise Integrated Communications Processor
79RC32334-150BBG 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDT Interprise Integrated Communications Processor
79RC32334-150BBGI 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDT Interprise Integrated Communications Processor
79RC32334-150BBI 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDT Interprise Integrated Communications Processor
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