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參數(shù)資料
| 型號： | 7951KWC |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Zero Delay Clock Multiplier |
| 中文描述： | 零延遲時鐘倍頻 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 72K |
| 代理商： | 7951KWC |
www.fairchildsemi.com
REV. 1.0.0 1/9/01
Features
Low Voltage CMOS or PECL reference input
Up to 175 MHz of output frequency
Nine configurable outputs
Output enable pin
250 pS of output to output skew
300 pS of Cycle to Cycle Jitter
V
DD
Range of 3.3V ±0.2V
Commercial temperature range
Available in 32 pin TQFP
Description
FMS7951 is a high speed, zero delay, low skew clock driver. It
uses phase locked loop technology to generate frequencies up
to 175 MHz.
It has four banks of configurable outputs. By externally con-
necting one of the outputs to FBIN, the internal PLL will
lock in both phase and frequency to the incoming clock. Any
changes to the input clock will be tracked by the outputs.
Depending on the selected output for feedback connection,
the output frequencies will be as 1X, 2X or 4X of the input.
REF_SEL allows selection between PECL input or TCLK a
CMOS clock driven input. Connecting PLL_EN LOW and
REF_SEL HIGH will by pass the Phase locked loop. In this
mode, FMS7951 will be in clock buffer mode where any
clock applied to TCLK will be divided down to the four out-
put banks. This is ideal for system diagnostic test. When
PLL_EN is HIGH, the PLL is enabled, and any clock applied
to TCLK will be locked in both phase and frequency to
FBIN. PECL_CLK is activated when REF_SEL is high.
FMS7951 operates at 3.3 Volts and is available in 32 pin LQFP.
FMS7951
Zero Delay Clock Multiplier
Block Diagram
MUX
MUX
DIV_SEL A
TCLK
FBIN
PECL_CLK
PECL_CLK
DIV_SEL B
DIV_SEL C
DIV_SEL D
QA
QB
QC0
QC1
QD0
QD1
QD2
QD3
QD4
OE
PLL
Control
Logic
PLL_EN
REF_SEL
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