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參數(shù)資料
| 型號： | 78Q2132 |
| 廠商： | TDK Corporation |
| 英文描述： | 1/10BASE-T HomePNA/Ethernet Transceiver |
| 中文描述： | 1/10BASE-T電話線網(wǎng)絡/以太網(wǎng)收發(fā)器 |
| 文件頁數(shù)： | 17/36頁 |
| 文件大?。?/td> | 172K |
| 代理商： | 78Q2132 |
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78Q2132
1/10BASE-TX
HomePNA/Ethernet Transceiver
17
MR16 - VENDOR SPECIFIC REGISTER
(continued)
BIT
16.6
SYMBOL
GPIO0_DIR
TYPE
R, W, 1
DESCRIPTION
GENERAL PURPOSE I/O 0 DIRECTION BIT: Setting this bit
configures the GPIO0 pin as an input. Resetting it configures GPIO0
as an output.
AUTO POLARITY: During auto-negotiation and 10BASE-T mode,
the 78Q2132 is able to automatically invert the received signal - both
the Manchester data and link pulses - if necessary. Setting this bit
disables this feature.
REVERSE POLARITY: The reverse polarity is detected through 8
inverted 10BASE-T link. When the reverse polarity is detected, the
78Q2132 will invert the receive data path and set this bit to logic one
if the feature is not disabled. If
APOL
is a logic 1, then this bit is
write-able. Setting this bit forces the polarity to be reversed.
RESERVED. Must be zero.
MII ENABLE: When this bit is high, the MII port mode is selected.
When low, its meaning is dependent on the mode of the chip as
shown below:
16.5
APOL
R, W, 0
16.4
RVSPOL
R, (W), 0
16.3:2
16.1
RSVD
MII_EN
R, 0
R,W,0
Mode
Function
Hi
MII
MII
Lo
HomeLAN
10BT
GPSI
MII
16.0
RSVD
R, 0
RESERVED. Must be zero.
MR17 - INTERRUPT CONTROL/STATUS REGISTER
The Interrupt Control/Status Register provides the means for controlling and observing the events that trigger an
interrupt on the INTR pin. This register can also be used in a polling mode via the MII serial interface as a means
to observe key events within the PHY via one register address. These bits are cleared after the register is read.
Bits 8-15 of this register, when set to logic one, enable their corresponding bit in the lower byte to signal an
interrupt on the INTR pin. The level of this interrupt can be set via MR16.14.
BIT
SYMBOL
TYPE
DESCRIPTION
17.15
JABBER IE
R, W, 0
Jabber Interrupt Enable
17.14
17.13
RXER IE
PRX IE
R, W, 0
R, W, 0
Receive Error Interrupt Enable: Reserved for 100Base-TX
Page Received Interrupt Enable
17.12
PDF IE
R, W, 0
Parallel Detect Fault Interrupt Enable
17.11
17.10
LP-ACK IE
LS-CHG IE
R, W, 0
R, W, 0
Link Partner Acknowledge Interrupt Enable
Link Status Change Interrupt Enable
17.9
RFAULT IE
R, W, 0
Remote Fault Interrupt Enable
17.8
17.7
ANEG-COMP IE
JABBER INT
R, W, 0
RC, 0
Auto-negotiation Complete Interrupt Enable
Jabber Interrupt: This bit is set when a jabber event is indicated by the
10baseT circuitry.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 78Q2133 | 制造商:Maxim Integrated Products 功能描述: |
| 78Q2133/F | 功能描述:以太網(wǎng) IC 10/100 Fast Ethernet MicroPHY RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| 78Q2133/F1 | 功能描述:以太網(wǎng) IC RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| 78Q2133-DB | 功能描述:以太網(wǎng)開發(fā)工具 78Q2133 Demo Brd RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
| 78Q2133-DIE | 制造商:Maxim Integrated Products 功能描述:78Q2133-DIE NOTE: MOQ = 10500 DIE (1 WAFER) - Gel-pak, waffle pack, wafer, diced wafer on film |
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