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參數(shù)資料
| 型號(hào)： | 78Q2123/F |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 8/38頁 |
| 文件大?。?/td> | 0K |
| 描述： | TXRX 10/100 MDIX 3.3V COMM 32QFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 490 |
| 類型： | PHY 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 4/4 |
| 規(guī)程： | IEEE 802 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-QFN 裸露焊盤（5x5） |
| 包裝： | 管件 |
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78Q2123/78Q2133 Data Sheet
DS_21x3_001
16
Rev. 1.6
3.2
MR1: Status Register
Bits 1.15 through 1.11 reflect the ability of the 78Q2123/78Q2133. They do not reflect any ability changes
made via the MII Management Interface to bits 0.13 (SPEEDSL) , 0.12 (ANEGEN) and 0.8 (DUPLEX) in
the Control Register.
Bit
Symbol
Type
Default
Description
1.15
100T4
R
0
100BASE-T4 Ability: Reads ‘0’ to indicate the
78Q2123/78Q2133 do not support 100Base-T4 mode.
1.14
100X_F
R
1
100BASE-TX Full Duplex Ability:
0 : Not able
1 : Able
1.13
100X_H
R
1
100BASE-TX Half Duplex Ability:
0 : Not able
1 : Able
1.12
10T_F
R
1
10BASE-T Full Duplex Ability:
0 : Not able
1 : Able
1.11
10T_H
R
1
10BASE-T Half Duplex Ability:
0 : Not able
1 : Able
1.10
100T2_F
R
0
100BASE-T2 Full Duplex Ability: Reads ‘0’ to indicate the
78Q2123/78Q2133 do not support 100Base-T2 full duplex
mode.
1.9
100T2_H
R
0
100BASE-T2 Half Duplex Ability: Reads ‘0’ to indicate the
78Q2123/78Q2133 do not support 100Base-T2 full duplex
mode.
1.8
EXTS
R
0
Extended Status Information Availability: Reads ‘0’ to indicate
the 78Q2123/78Q2133 do not support Extended Status
information on MR15.
1.7
RSVD
R
0
Reserved
1.6
MFPS
R
0
Management Frame Preamble Suppression Support: A “0”
indicates that the 78Q2123/78Q2133 can read management
frames with a preamble.
1.5
ANEGC
R
0
Auto-Negotiation Complete: A logic one indicates that the
Auto-Negotiation process has been completed, and that the
contents of registers MR4,5,6 are valid.
1.4
RFAULT
RC
0
Remote Fault: A logic one indicates that a remote fault
condition has been detected and it remains set until it is
cleared. This bit can only be cleared by reading this register
(MR1) via the management interface.
1.3
ANEGA
R
(1)
Auto-Negotiation Ability: When set, this bit indicates the
device’s ability to perform Auto-Negotiation. The value of this
bit is determined by the
ANEGEN bit (MR0.12).
1.2
LINK
R
0
Link Status: A logic one indicates that a valid link has been
established. If the link status should transition from an OK
status to a NOT-OK status, this bit will become cleared and
remains cleared until it is read.
1.1
JAB
RC
0
Jabber Detect: In 10Base-T mode, this bit is set during a
jabber event. After a jabber event, the bit remains set until
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| 78Q2123R/F | 功能描述:以太網(wǎng) IC 10/100 Fast Ethernet MicroPHY RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| 78Q2123R/F1 | 功能描述:以太網(wǎng) IC RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| 78Q2123S/F | 功能描述:1/1 Transceiver Full Ethernet 16-TQFN (5x5) 制造商:maxim integrated 系列:MicroPHY?? 包裝:管件 零件狀態(tài):有效 類型:收發(fā)器 協(xié)議:以太網(wǎng) 驅(qū)動(dòng)器/接收器數(shù):1/1 雙工:全 接收器滯后:- 數(shù)據(jù)速率:- 電壓 - 電源:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-WQFN 裸露焊盤 供應(yīng)商器件封裝:16-TQFN（5x5） 標(biāo)準(zhǔn)包裝:60 |
| 78Q2123SR/F | 功能描述:1/1 Transceiver Full Ethernet 16-TQFN (5x5) 制造商:maxim integrated 系列:MicroPHY?? 包裝:帶卷（TR） 零件狀態(tài):有效 類型:收發(fā)器 協(xié)議:以太網(wǎng) 驅(qū)動(dòng)器/接收器數(shù):1/1 雙工:全 接收器滯后:- 數(shù)據(jù)速率:- 電壓 - 電源:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-WQFN 裸露焊盤 供應(yīng)商器件封裝:16-TQFN（5x5） 標(biāo)準(zhǔn)包裝:2,500 |
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