參數(shù)資料
型號(hào)： 78Q2120-CGT
廠商： Electronic Theatre Controls, Inc.
英文描述： 10/100BASE-TX Ethernet Transceiver
中文描述： 10/100BASE-TX以太網(wǎng)收發(fā)器
文件頁(yè)數(shù)： 9/33頁(yè)
文件大?。?/td> 200K
代理商： 78Q2120-CGT
78Q2120
10/100BASE-TX
Ethernet Transceiver
OSCILLATOR/CLOCK
9
NAME
64-PIN
80-PIN
TYPE
DESCRIPTION
CKIN
4
5
I
CLOCK INPUT: Connects to a 25 MHz clock source. This pin should
be held low when XTLP and XTLN are being used as the 25 MHz
clock source.
XTLP,
XTLN
59, 58
75,74
A
CRYSTAL PINS: Should be connected to a 25 MHz crystal. When
CKIN is being used as the 25 MHz clock source, these pins should be
connected together.
MISCELLANEOUS PINS
GPIO0
-
19
I/O
GENERAL PURPOSE I/O PIN: This is an I/O pin which is
configurable as an input or an output via management interface. A
value of one in bit MR16.6 configures GPIO0 as an input, and a zero
configures it as an output. The logic level of the GPIO0 pin is reflected
in MR16.7. This pin has a weak internal pull-down to prevent it from
floating when configured as an input (it is configured as an input by
default).
GPIO1
-
20
I/O
GENERAL PURPOSE I/O PIN: This is an I/O pin which is
configurable as an input or an output via the management interface. A
value of one in bit MR16.8 configures GPIO1 as an input, and a zero
configures it as an output. The logic level of the GPIO1 pin is reflected
in MR16.9. This pin has a weak internal pull-down to prevent it from
floating when configured as an input (it is configured as an input by
default).
INTR
35
43
OZ
INTERRUPT PIN: This pin is used to signal an interrupt to the media
access controller. The pin is held in the high impedance state when
an interrupt is not indicated. The pin will be forced high or low to
signal an interrupt depending upon the value of the INTR_LEVEL bt
(MR16.14). The events which trigger an interrupt can be programmed
via the Interrupt Control Register located at address MR17.
POWER SUPPLY
V
CC
8, 11,
41, 43,
57, 63
10,13,
27,36, 49,
52, 59, 60,
73, 79 80
S
SUPPLY VOLTAGE: Two supply ranges are supported: 5V
±
0.5V, or
3.3V
±
0.3V.
GND
3, 5, 9,
10, 42,
53, 55,
60
4,7, 11,12,
28, 35, 50,
51, 65, 71,
76
S
GROUND
REFERENCE PIN
RIBB
56
72
A
BIAS CURRENT SETTING RESISTOR: To be tied to an external
resistor which is also connected to pin 70. This resistor should be
placed as close as possible to the package pin. See Figure 1 for
suggested value.
RIBB_RET
54
70
A
BIAS CURRENT SETTING RESISTOR RETURN PIN: To be
connected to external RIBB resistor.
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