參數(shù)資料
型號(hào)： 78M6613-IMR/F/P
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 電源管理
英文描述： 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC32
封裝： 5 X 5 MM, ROHS COMPLIANT, QFN-32
文件頁(yè)數(shù)： 32/33頁(yè)
文件大?。?/td> 957K
代理商： 78M6613-IMR/F/P
78M6613 Data Sheet
DS_6613_018
8
Rev. 1.1
1.3
Digital Computation Engine (CE)
The CE, a dedicated 32-bit signal processor, performs the precision computations necessary to
accurately measure energy. The CE calculations and processes include:
Multiplication of each current sample with its associated voltage sample to obtain the energy per
sample (when multiplied with the constant sample time).
Frequency-insensitive delay cancellation on all channels (to compensate for the delay between
samples caused by the multiplexing scheme).
90° phase shifter (for narrowband VARh calculations).
Monitoring of the input signal frequency (for frequency and phase information).
Monitoring of the input signal amplitude (for sag detection).
Scaling of the processed samples based on calibration coefficients.
CE code is provided by Teridian as a part of the application firmware available. The CE is not
programmable by the user. Measurement algorithms in the CE code can be customized by
Teridian upon request.
The CE program resides in Flash memory. Common access to Flash memory by CE and MPU is
controlled by a memory share circuit. Allocated Flash space for the CE program cannot exceed 1024
words (2KB).
The CE DRAM can be accessed by the CE and the MPU. Holding registers are used to convert 8-bit
wide MPU data to/from 32-bit wide CE DRAM data, and wait states are inserted as needed, depending
on the frequency of CKMPU. The CE DRAM contains 128 32-bit words. The MPU can read and write
the CE DRAM as the primary means of data communication between the two processors. CE hardware
issues an interrupt when accumulation is complete.
1.4
80515 MPU Core
The 78M6613 includes an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one
clock cycle. Using a 5 MHz (4.9152 MHz) clock results in a processing throughput of 5 MIPS. The
80515 architecture eliminates redundant bus states and implements parallel execution of fetch and
execution phases. Normally a machine cycle is aligned with a memory fetch, therefore, most of the
1-byte instructions are performed in a single cycle. This leads to an 8x performance (in average)
improvement (in terms of MIPS) over the Intel 8051 device running at the same clock frequency. Actual
processor clocking speed can be adjusted to the total processing demand of the application
(measurement calculations, memory management and I/O management).
Typical power and energy measurement functions based on the results provided by the internal
32-bit compute engine (CE) are available for the MPU as part of Teridian’s standard library.
MPU Memory Organization, Special Function Registers, Interrupts, Counters, and other controls
are described in the applicable firmware documentation.
1.4.1
UART
The 78M6613 includes a UART that can be programmed to communicate with a variety of external
devices. The UART is a dedicated 2-wire serial interface, which can communicate with an external
device at up to 38,400 bits/s. All UART transfers are programmable for parity enable, parity, 2 stop
bits/1 stop bit and XON/XOFF options for variable communication baud rates from 300 to 38,400 bps.
相關(guān)PDF資料
PDF描述
78M6613-IM/F 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC32
7901502EA 4-CHANNEL, DIFFERENTIAL MULTIPLEXER, CDIP16
798R07-001 SPECIALTY CONSUMER CIRCUIT, SMA
7MBP100RTJ060 AC MOTOR CONTROLLER, 200 A, XMA25
7WB383DMR2G SGL ENDED MULTIPLEXER, PDSO8
相關(guān)代理商/技術(shù)參數(shù)
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