參數(shù)資料
型號(hào)： 7846ARPFS
廠商： MAXWELL TECHNOLOGIES
元件分類(lèi)： DAC
英文描述： 16-Bit Digital to Analog Converter
中文描述： PARALLEL, WORD INPUT LOADING, 9 us SETTLING TIME, 16-BIT DAC, DFP28
封裝： RAD PAK, LDFP-28
文件頁(yè)數(shù)： 6/11頁(yè)
文件大?。?/td> 256K
代理商： 7846ARPFS
M
6
All data sheets are subject to change without notice
2003 Maxwell Technologies
All rights reserved.
16-Bit Digital to Analog Converter
7846A
05.29.03 REV 5
T
ABLE
6. 7846A T
IMING
C
HARACTERISTICS1,2,3,4
(V
DD
= +14.25V
TO
15.75V; V
SS
= -14.25V
TO
-15.75V; V
CC
= 4.75
TO
5.25V;
UNLESS
OTHERWISE
SPECIFIED
)
1. Guaranteed by design. All input control signals are specified with t
R
= t
F
= 5ns (10% to 90% of +5V) and timed froma voltage
level of 1.6V.
2. t
6
is measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V.
3. t
7
is defined as the time required for an output to change 0.5V when loaded with the circuits of Figure 2. Specifications subject to
change without notice.
4. See Figure 3 on page 7.
P
ARAMETER
T
EST
C
ONDITIONS
/C
OMMENTS
L
IMIT
A
T
T
A
=-55
°
C
TO
+125
°
C
U
NIT
t
1
t
2
t
3
t
4
t
5
t
6
t
7
R/W to CS Setup Time
50
ns mn
CS Pulse Width (Write Cycle)
190
ns mn
R/W to CS Hold Time
50
ns mn
Data Setup Time
120
ns mn
Data Hold Time
0
ns mn
Data Access Time
320
ns max
Bus Relinquish Time
10
ns mn
90
ns max
t
8
t
9
t
10
t
11
t
12
CLR Setup Time
20
ns mn
CLR Pulse Width
150
ns mn
CLR Hold Time
0
ns mn
LDAC Pulse Width
100
ns mn
CS Pulse Width (Read Cycle)
330
ns mn
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