參數(shù)資料
型號: 784217A
廠商: NEC Corp.
英文描述: MOS INTEGRATED CIRCUIT
中文描述: 馬鞍山集成電路
文件頁數(shù): 75/100頁
文件大?。?/td> 564K
代理商: 784217A
Data Sheet U14121EJ2V0DS00
75
μ
PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
www.DataSheet4U.com
AC Characteristics (T
A
=
40 to +85
°
C, V
DD
= AV
DD
= 1.8 to 5.5 V, V
SS
= AV
SS
= 0 V)
(1) Read/write operation (1/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
4.5 V
V
DD
5.5 V
80
ns
2.7 V
V
DD
<
4.5 V
160
ns
2.0 V
V
DD
<
2.7 V
320
ns
Cycle time
t
CYK
1.8 V
V
DD
<
2.0 V
500
ns
V
DD
= 5.0 V
±
10%
(0.5
+
a)T
20
ns
V
DD
= 3.0 V
±
10%
(0.5
+
a)T
40
ns
Address setup time (to ASTB
)
t
SAST
V
DD
= 2.0 V
±
10%
(0.5
+
a)T
80
ns
V
DD
= 5.0 V
±
10%
0.5T
19
ns
V
DD
= 3.0 V
±
10%
0.5T
24
ns
Address hold time (from ASTB
) t
HSTLA
V
DD
= 2.0 V
±
10%
0.5T
34
ns
V
DD
= 5.0 V
±
10%
(0.5
+
a)T
17
ns
V
DD
= 3.0 V
±
10%
(0.5
+
a)T
40
ns
ASTB high-level width
t
WSTH
V
DD
= 2.0 V
±
10%
(0.5
+
a)T
110
ns
V
DD
= 5.0 V
±
10%
0.5T
14
ns
V
DD
= 3.0 V
±
10%
0.5T
14
ns
Address hold time (from RD
)
t
HRA
V
DD
= 2.0 V
±
10%
0.5T
14
ns
V
DD
= 5.0 V
±
10%
(1
+
a)T
24
ns
V
DD
= 3.0 V
±
10%
(1
+
a)T
35
ns
Delay time from address to RD
t
DAR
V
DD
= 2.0 V
±
10%
(1
+
a)T
80
ns
V
DD
= 5.0 V
±
10%
0
ns
V
DD
= 3.0 V
±
10%
0
ns
Address float time (from RD
)
t
FAR
V
DD
= 2.0 V
±
10%
0
ns
V
DD
= 5.0 V
±
10%
(2.5
+
a
+
n)T
37
ns
V
DD
= 3.0 V
±
10%
(2.5
+
a
+
n)T
52
ns
Data input time from address
t
DAID
V
DD
= 2.0 V
±
10%
(2.5
+
a
+
n)T
120
ns
V
DD
= 5.0 V
±
10%
(2
+
n)T
35
ns
V
DD
= 3.0 V
±
10%
(2
+
n)T
50
ns
Data input time from ASTB
t
DSTID
V
DD
= 2.0 V
±
10%
(2
+
n)T
80
ns
V
DD
= 5.0 V
±
10%
(1.5
+
n)T
40
ns
V
DD
= 3.0 V
±
10%
(1.5
+
n)T
50
ns
Data input time from RD
t
DRID
V
DD
= 2.0 V
±
10%
(1.5
+
n)T
90
ns
V
DD
= 5.0 V
±
10%
0.5T
9
ns
V
DD
= 3.0 V
±
10%
0.5T
9
ns
Delay time from ASTB
to RD
t
DSTR
V
DD
= 2.0 V
±
10%
0.5T
20
ns
V
DD
= 5.0 V
±
10%
0
ns
V
DD
= 3.0 V
±
10%
0
ns
Data hold time (from RD
)
t
HRID
V
DD
= 2.0 V
±
10%
0
ns
Remark
T: t
CYK
= 1/f
XX
(f
XX
: main system clock frequency)
a: 1 (during address wait), otherwise, 0
n: Number of waits (n
0)
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