參數(shù)資料
型號(hào)： 7809LPRPFH
廠商： MAXWELL TECHNOLOGIES
元件分類： ADC
英文描述： 16-Bit Latchup Protected Analog to Digital Converter
中文描述： 3-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, DFP24
封裝： FP-24
文件頁(yè)數(shù)： 15/23頁(yè)
文件大?。?/td> 462K
代理商： 7809LPRPFH
M
15
All data sheets are subject to change without notice
2005 Maxwell Technologies
All rights reserved.
16-Bit Latchup Protected Analog to Digital Converter
7809LP
01.11.05 Rev 7
Differences Between the 7809LP and the ADS7809
Because the 7809LP uses the ADS7809 die to performthe analog to digital conversion function, its operation and per-
formance is very simlar to the ADS7809 packaged part fromBurr-Brown. In general the operation and application will
be the same for both parts. There are three primary differences: the operation of the supply pins, the operation of the
additional LPBIT and LPSTATUS pins, and the operation of the I/O pins when a latchup is detected.
The ADS7809 provides separate analog and digital supply pins, VANA and VDIG. These same supply pins on the
7809LPRP should be connected to the analog and digital supplies. There is no limt to the capacitance that can be
connected to these pins in the systemapplication.
The 7809LP package also provides access to the ADS7809 die supply pins with the LPVANA and LPVDIG pins. The
signal paths between the supply input pins and the respective die supply pins are low resistance during normal device
operation. When an excessive supply current due to a single event latchup is sensed on either of the supply pins, the
LPT
TM
circuit opens both paths to the die supply pins allowing the latchup condition to clear. The LPVANA and LPV-
DIG pins allow access to the current sense circuitry for electrical testing at the component level and provide optimal
locations for attaching supply decoupling capacitors.
CAUTION:
The LPVANA and LPVDIG pins must not be con-
nected to the respective power supplies since this will defeat the LPT
TM
power switch and could result in permanent
latchup of the device during operation in a radiation environment. Electrolytic capacitors should not be connected to
these decoupling pins because the large capacitance will increase the recovery time of the 7809LP. Low ESR ceramc
capacitors should be used with a maximumof .2μF per pin.
The LPBIT input provides a means to electrically test the LPT
TM
circuit. A high level on the this pin causes a preset
current to be drawn in addition to the normal device current through the analog and digital current sensors. If the high
level is maintained for a sufficient duration, it will trigger the LPT
TM
circuit which will cycle the power to the protected
device. If the LPBIT remains high, the LPT
TM
circuit will continuously cycle the supply voltages off then on. Driving this
input with a 10 μs high level pulse is sufficient duration to assure the LPT
TM
circuit cycles the power off then on one
time only.
A high level on the LPSTATUS output indicates that the LPT
TM
circuit has removed power fromthe protected device.
The LPSTATUS returns low when the power is restored. LPSTATUS can be used to generate an input to the system
data processor indicating that an LPT
TM
cycle has occurred and the protected device output accuracy may not be met
until after the respective recovery time to the event.
During the time that power is removed fromthe protected device, it is critical that external circuitry driving the device I/
O pins does not back-drive the device supply through input protection diodes or simlar integrated structures. Back-
driving of the supply through the device I/O pins could contribute to an extended or even a permanent latchup condi-
tion. For the ADS7809 testing has shown that for the normal signal range of operation on the analog input pins R1IN,
R2IN, and R3IN, latchup will not be sustained.
In order to prevent back-driving the supply fromthe digital I/O pins DATA, SYNC, TAG, R/C, CS, and PWRD, the
7809LP incorporates active input protection circuits. These circuits act as transmssion gates in series with the digital
inputs. During normal operation, these gates are on and present low resistance connections between the package
input pins and the respective die pins. When the LPT
TM
circuit detects a latchup, these gates are switched off and
present a high resistance path between the package inputs and the die inputs. The protected I/O pins are crow barred
during the latchup. The bidirectional signal, DATACLK, is also protected by a transmssion gate.
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