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參數(shù)資料
| 型號(hào)： | 7809LPRPFE |
| 廠商： | MAXWELL TECHNOLOGIES |
| 元件分類： | ADC |
| 英文描述： | 16-Bit Latchup Protected Analog to Digital Converter |
| 中文描述： | 3-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, DFP24 |
| 封裝： | FP-24 |
| 文件頁數(shù)： | 7/23頁 |
| 文件大?。?/td> | 462K |
| 代理商： | 7809LPRPFE |
M
7
All data sheets are subject to change without notice
2005 Maxwell Technologies
All rights reserved.
16-Bit Latchup Protected Analog to Digital Converter
7809LP
01.11.05 Rev 7
T
ABLE
12. 7809LP C
ONTROL
L
INE
F
UNCTIONS
FOR
R
EAD
AND
C
ONVERT
S
PECIFIC
F
UNCTION
CS
R/C
BUSY
EXT/INT
DATACL
K
PWRD
SB/BTC
O
PERATION
Initiate Conver-
sion and Output
Data using Inter-
nal Clock
1 > 0
0
0
1 > 0
1
1
0
0
Output
Output
0
0
x
x
Initiates conversion “n”.
Data fromconversion “n-
1” clocked out on DATA
synchronized to 16 clock
pulses output on DATA-
CLK
Initiates conversion “n”.
Data fromconversion “n-
1” clocked out on DATA
synchronized to 16 clock
pulses output on DATA-
CLK
Initiates conversion “n”
Initiates conversion “n”
Outputs a pulse on SYNC
followed by data fromcon-
version “n” clocked out
synchronized to external
DATACLK.
Outputs a pules on SYNC
followed by data fromcon-
version “n-1” clocked out
synchronized to external
DATACLK
1
. Conversion
“n” in process.
Outputs a pulse on SYNC
followed by data fromcon-
version “n-1” clocked out
synchronized to external
DATACLK
1
. Conversion
“n” in process.
CS or R/C must be HIGH
or a new conversion will
be initiated without time
for acquisition
Analog circuitry powered.
Conversion will be initi-
ated without time for
acquisition
Analog circuitry disabled.
Data fromprevious con-
version maintained in out-
put registers
Initiate Conver-
sion and Output
Data using Exter-
nal Clock
1 > 0
0
1 > 0
1 > 0
0
0
1 > 0
1
1
0 > 1
1
1
1
0
0
1
1
1
1
1
Input
Input
Input
Input
Input
0
0
x
0
0
x
x
x
x
x
Incorrect Conver-
sions
0
0
0 > 1
x
x
0
x
Power Down
x
x
x
x
x
x
x
x
x
x
0
1
x
x
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