45
CHAPTER 4 INSTRUCTION SET
User's Manual U12326EJ4V0UM
Unconditional
BR
!addr16
1 0 0 1
1 0 1 1
Low addr
High addr
Branch
$addr16
1 1 1 1
1 0 1 0
jdisp
AX
0 0 1 1
0 0 0 1
1 0 0 1
1 0 0 0
Conditional
BC
$addr16
1 0 0 0
1 1 0 1
jdisp
Branch
BNC
$addr16
1 0 0 1
1 1 0 1
jdisp
BZ
$addr16
1 0 1 0
1 1 0 1
jdisp
BNZ
$addr16
1 0 1 1
1 1 0 1
jdisp
BT
saddr.bit,$addr16
1
B
2
B
1
B
0
1 1 0 0
Saddr-offset
jdisp
sfr.bit,$addr16
0 0 1 1
0 0 0 1
0
B
2
B
1
B
0
0 1 1 0
Sfr-offset
jdisp
A.bit,$addr16
0 0 1 1
0 0 0 1
0
B
2
B
1
B
0
1 1 1 0
jdisp
PSW.bit,$addr16
1
B
2
B
1
B
0
1 1 0 0
0 0 0 1
1 1 1 0
jdisp
[HL].bit,$addr16
0 0 1 1
0 0 0 1
1
B
2
B
1
B
0
0 1 1 0
jdisp
BF
saddr.bit,$addr16
0 0 1 1
0 0 0 1
0
B
2
B
1
B
0
0 0 1 1
Saddr-offset
jdisp
sfr.bit,$addr16
0 0 1 1
0 0 0 1
0
B
2
B
1
B
0
0 1 1 1
Sfr-offset
jdisp
A.bit,$addr16
0 0 1 1
0 0 0 1
0
B
2
B
1
B
0
1 1 1 1
jdisp
PSW.bit,$addr16
0 0 1 1
0 0 0 1
0
B
2
B
1
B
0
0 0 1 1
0 0 0 1
1 1 1 0
jdisp
[HL].bit,$addr16
0 0 1 1
0 0 0 1
1
B
2
B
1
B
0
0 1 1 1
jdisp
BTCLR
saddr.bit,$addr16
0 0 1 1
0 0 0 1
0
B
2
B
1
B
0
0 0 0 1
Saddr-offset
jdisp
sfr.bit,$addr16
0 0 1 1
0 0 0 1
0
B
2
B
1
B
0
0 1 0 1
Sfr-offset
jdisp
A.bit,$addr16
0 0 1 1
0 0 0 1
0
B
2
B
1
B
0
1 1 0 1
jdisp
PSW.bit,$addr16
0 0 1 1
0 0 0 1
0
B
2
B
1
B
0
0 0 0 1
0 0 0 1
1 1 1 0
jdisp
[HL].bit,$addr16
0 0 1 1
0 0 0 1
1
B
2
B
1
B
0
0 1 0 1
jdisp
DBNZ
B,$addr16
1 0 0 0
1 0 1 1
jdisp
C,$addr16
1 0 0 0
1 0 1 0
jdisp
saddr,$addr16
0 0 0 0
0 1 0 0
Saddr-offset
jdisp
CPU
SEL
RBn
0 1 1 0
0 0 0 1
1 1
RB
1
1
RB
0
0 0 0
control
NOP
0 0 0 0
0 0 0 0
EI
0 1 1 1
1 0 1 0
0 0 0 1
1 1 1 0
DI
0 1 1 1
1 0 1 1
0 0 0 1
1 1 1 0
HALT
0 1 1 1
0 0 0 1
0 0 0 1
0 0 0 0
STOP
0 1 1 1
0 0 0 1
0 0 0 0
0 0 0 0
Instruction
Mnemonic
Operands
Operation Code
Group
B1
B2
B3
B4