參數(shù)資料
型號: 7805ALPRPFB
廠商: MAXWELL TECHNOLOGIES
元件分類: ADC
英文描述: 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, DFP28
封裝: RAD-PAK, LDFP-28
文件頁數(shù): 15/34頁
文件大小: 605K
代理商: 7805ALPRPFB
Memory
PRELIMINARY
22
All data sheets are subject to change without notice
2001 Maxwell Technologies
All rights reserved.
16-Bit Latchup Protected ADC
7805ALP
12.19.01 Rev 6
1000583
FIGURE 19. CLR FUNCTIONS FOR MAIN AND SUB DACS
POWER-DOWN AND STANDBY FUNCTIONS
There are two distinct low power modes on the device, powerdown mode and standby mode. When in power-down
mode all circuitry including the reference are put into low power mode and power dissipation from the package is at its
minimum.
FIGURE 20. IMPLEMENTATION OF POWER-DOWN AND STANDBY FUNCTIONS
The standby functions allow either the selected DAC or all DACs in the package to be put into low power mode. The
reference is not switched off when any of the standby functions are invoked.
The PD bit in the system control register is used to shut down the complete device. With a 0 in this position the refer-
ence and all DACs are put into low power mode. Writing a 1 to this bit puts the part in the normal operating mode.
When in power-down mode the contents of all registers are retained and are valid when the device is taken out of
power down. The SSTBY bit which resides in the system control register can be used to put all DACs and their associ-
ated linear circuitry into standby mode, the SSTBY function does not power down the reference. The STBY bit in the
channel control register can be used to put a selected DAC and its associated linear circuitry into standby mode. Fig-
ure 18 shows a simplified diagram of how the power-down and standby functions are implemented for a single DAC in
the package.
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參數(shù)描述
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