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參數(shù)資料
| 型號： | 7805ALPRPDI |
| 廠商： | MAXWELL TECHNOLOGIES |
| 元件分類： | ADC |
| 英文描述： | 16-Bit Latchup Protected ADC |
| 中文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, DIP28 |
| 封裝： | DIP-28 |
| 文件頁數(shù)： | 10/18頁 |
| 文件大小： | 262K |
| 代理商： | 7805ALPRPDI |
M
10
All data sheets are subject to change without notice
2005 Maxwell Technologies
All rights reserved.
16-Bit Latchup Protected ADC
7805ALP
01.10.05 Rev 9
In order to prevent backdriving the supply, the STATUS signal should be used in the systemto tri-state or gate external
I/O drive circuits to a low state. Simlarly, if the data outputs are connected to a bus with other bus driver circuits, all
external data bus drivers must be tri-stated and individual pull up resistors to the supply voltage (if used on the data
bus) must not be less than 10 K
typical to assure proper single event effect recovery. Tri-stating of inputs should
occur within 100 nsec after the rise of the status pin. The BYTE signal can be made available in place of the STATUS
signal at customer request.
STATUS can also be used to generate an input to the systemdata processor indicating that an LPT
cycle has
occurred, and the protected device output accuracy may not be met until after the respective recovery time to the
event. The STATUS signal is generated froman advanced CMOS logic gate output. This output may not exhibit a
monotonic falltime and may even oscillate briefly while power is being restored to the protected device and the decou-
pling capacitance is charged. Loading on the STATUS output should be mnimzed because this signal is used inter-
nally by the 7805A. It is recommended that load current not exceed 2 mA and load capacitance be kept well below
1000 pF.
A summary of the pin differences between the ADS7805 and 7805A is provided below
Example Circuits for Using the 7805A
Figure 2 shows a typical application circuit for using the 7805A as an input to a digital data processor. This circuit
shows the use of the STATUS pin to tri-state the control inputs when the latchup protection circuit cycles the power to
the protected ADS7805 die.
Figure 3 shows a typical application circuit for connecting the 7805A to a 16-bit data bus with multiple drivers on the
bus. Tri-state buffers are used to isolate the 7805A data outputs fromthe data bus. Figure 4 shows the typical applica-
tion circuit for connecting the 7805A to an 8-bit data bus.
T
ABLE
16. P
IN
D
IFFERENCES
P
IN
N
UMBER
ADS7805
7805A
P
IN
D
IFFERENCE
D
ESCRIPTION
23
BYTE
STATUS
A high level STATUS signal indicates that power is removed fromthe ADS7805 die.
I/O pins must not be driven high while this signal is active. The BYTE signal of the
ADS7805 die is internally grounded but can also be made available in place of the
STATUS pin at customer request.
The ADS7805 VANA and V
DIG
die pads are connected together and are available
at the DECPLNG pin. This pin allows external ceramc capacitors to directly decou-
ple the power inputs to the ADS7805 die-to-analog ground. Decoupling capaci-
tance should not exceed 0.2 uF typical. This pin must not be connected to a power
supply directly since this will defeat the latchup protection circuitry. Electrolytic filter
capacitors should not be connected to this pin but should be connected between
the V
S
pin and ground.
This is the power supply input for the LPT circuitry and the protected ADS7805 die.
This supply should be treated as an analog supply with filtering and/or isolation
fromthe noisy systemdigital power supply. The LPT latchup current sense and
power switch circuitry is located between this pin and the DECPLNG pin.
27
VANA
DECPLNG
28
V
DIG
V
S
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