參數(shù)資料
型號: 780024
廠商: NEC Corp.
英文描述: Common to 78K/0 Series
中文描述: 共同的78K / 0系列
文件頁數(shù): 83/129頁
文件大?。?/td> 644K
代理商: 780024
CHAPTER 5 EXPLANATION OF INSTRUCTIONS
83
User's Manual U12326EJ4V0UM
Decimal Adjust Register for Addition
ADJBA
Decimal Adjustment of Addition Result
[Instruction format]
ADJBA
[Operation]
Decimal Adjust Accumulator for Addition
[Operand]
None
[Flag]
Z
AC
CY
×
×
×
[Description]
The A register, CY flag and AC flag are decimally adjusted from their contents. This instruction carries out
an operation having meaning only when the BCD (binary coded decimal) data is added and the addition result
is stored in the A register (in all other cases, the instruction carries out an operation having no meaning).
See the table below for the adjustment method.
If the adjustment result shows that the A register contents are 0, the Z flag is set (1). In all other cases,
the Z flag is cleared (0).
Condition
Operation
A
3
to A
0
9
A
7
to A
4
9 and CY = 0
A
A, CY
0, AC
0
AC = 0
A
7
to A
4
10 or CY = 1
A
A+01100000B, CY
1, AC
0
A
3
to A
0
10
A
7
to A
4
< 9 and CY = 0
A
A+00000110B, CY
0, AC
1
AC = 0
A
7
to A
4
9 or CY = 1
A
A+01100110B, CY
1, AC
1
AC = 1
A
7
to A
4
9 and CY = 0
A
A+00000110B, CY
0, AC
0
A
7
to A
4
10 or CY = 1
A
A+01100110B, CY
1, AC
0
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