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參數(shù)資料
| 型號： | 77LD1-12C110-01 |
| 英文描述： | Converter |
| 中文描述： | 轉(zhuǎn)換器 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 297K |
| 代理商： | 77LD1-12C110-01 |
Apex Signal,
A Division of NAI, Inc.
631.567.1100/631.567.1823(fax) 1-31-01 S 77 LD1 A001 REV B 1.2
170 Wilbur Place, Bohemia, NY, 11716,USA
www.naii.com
/ e-mail:sales@naii.com Code:OVGU1 Page 5 of 7
Signal and Reference
The LVDT primary is energized by either the on-board excitation or from an external excitation. The 4-wire or 3-wire
LVDT has two output voltages referred to as A and B. When connected to the A and B Signal inputs no scaling is
required because the inputs are autoranging, however the Signal registers can be used to scale the output code.
Default settings for the Signal Registers at page 2 are FFFFh. This results in a full scale output reading for full travel
of the LVDT. A full scale output reading for less than full travel of the LVDT can be programmed by writing to the
Signal Registers on page 2. For example, writing 8000h to page 2, 00/01h will result in channel 1 having a full scale
output reading for one-half travel of the LVDT.
For 2 wire Inputs, the Signal register can be used to adjust what fraction of the excitation voltage represents “full
travel” of the LVDT.
Optional Reference Supply:
For frequency, write a 16-bit word ( ex: 400 Hz = 1 1001 0000) at Page 7,
OAh/OBh. For voltage, write a word ( ex: 26.1 Vrms = 1 0000 0101) with LSB = 0.1 Vrms, to address Page 7,
OCh/ODh . It is recommended that the user program the required frequency before setting the output voltage.
Selecting 2 or 3,4 Wire operation:
Program the proper channel in the appropriate register on page 7,10h.
Logic 1 = 2 wire and logic 0 = 3,4 wire.
Read (A+B) output
:
:
Read binary number at appropriate register on page 6, and multiply by 0.01 Volt. For 2 wire
Inputs, this represents the B voltage.
Latch:
All channels may be latched by writing “1” to D1 at Page 7, 14h. Reading channel will disengage latch.
D2 Test Enable:
Writing “1” to D2 at page 7, 00h initiates automatic background BIT testing. Each channel is
checked over the programmed Signal range to a measuring accuracy 0.1%FS, and each Signal and Excitation is
monitored. The results are available in Status Registers. The testing is totally transparent to the user,
requires no external programming, has no effect on the standard operation of this card and can be enabled or
disabled via the bus. The card will write 55h to page 7, 02h when D2 is enabled. User can periodically clear to
0000h and then read page 7, 02h again, after 30 seconds, to verify that background BIT testing is activated.
Status, Test:
Check the corresponding bit of the Test Status Register at page 1, 1Ch/1Dh for status of BIT testing
for each active channel. A ”1” = Accuracy OK; “0” = failed. (test cycle takes 45 seconds for accuracy error).
Status, Exc:
Check the corresponding bit of the Exc Status Register at page 1, 1AH/1Bh for status of the
excitation input for each active channel. A ”1” = Exc. ON, “0” = Exc. Loss (Excitation loss is detected after 2
seconds).
Status, Sig:
Check the corresponding bit of the Sig Status Register at page 1, 18h/19h for status of the input
signals for each active channel. A "1" = Signal ON, “0” = Signal loss (Signal loss is detected after 2 seconds).
D3 Test Enable:
Writing “1” to D3 of Test Register at page7, 00h,
initiates a BIT test
that disconnects all channels
from the outside world and connects them across an internal stimulus that generates multiple test voltages that are
measured to a test accuracy of 0.1%FS. Test cycle takes about 45 seconds and results can be read from the Status
Registers when D3 changes from “1” to “0”. External excitation is not required. Testing requires no external
programming and can be initiated or terminated (by setting D3 to “0”) via the bus.
D0 Test Enable:
Checks the card and the PCbus interface. Writing “1” to D0 at page 7, 00h disconnects all
channels from the outside world, allowing user to write any number of input positions to the card at page 7 06/07h
and then read the data from the PCbus interface (allow 400 ms after writing). External excitation is not required.
NOTE:
The DO test will follow the program of channel 1: if channel 1 is programmed for 2 wire, then all channels will
be tested in the 2 wire mode. If channel 1 is programmed for 3,4 wire, then all channels will be tested in the 3,4 wire
mode.
If the card is set up as a mix of 2 and 3,4 wire channels, then chan 1 must be set as 2 wire (and all channels will be
tested with the appropriate channels passing ) and then chan 1 set as 3,4 wire ( and all channels will be tested with
the appropriate channels passing ).
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