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參數資料
| 型號： | 7660S |
| 廠商： | Intersil Corporation |
| 英文描述： | Super Voltage Converter |
| 中文描述： | 超電壓轉換器 |
| 文件頁數： | 7/9頁 |
| 文件大小： | 77K |
| 代理商： | 7660S |
3-42
enough to fully charge the capacitors every cycle. In a typical
application where f
OSC
= 10kHz and C = C
1
= C
2
= 10
μ
F:
1
(5 x 10
3
x 10 x 10
-6
)
Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5, a high value could
potentially swamp out a low 1/f
PUMP
x C
1
) term, rendering
an increase in switching frequency or filter capacitance
ineffective. Typical electrolytic capacitors may have ESRs as
high as 10
.
Output Ripple
ESR also affects the ripple voltage seen at the output. The
total ripple is determined by 2 voltages, A and B, as shown in
Figure 15. Segment A is the voltage drop across the ESR of
C
2
at the instant it goes from being charged by C
1
(current
flowing into C
2
) to being discharged through the load
(current flowing out of C
2
). The magnitude of this current
change is 2 x I
OUT
, hence the total drop is 2 x I
OUT
x
ESR
C2
V. Segment B is the voltage change across C
2
during
time t
2
, the half of the cycle when C
2
supplies current the
load. The drop at B is I
OUT
x t
2
/C
2
V. The peak-to-peak ripple
voltage is the sum of these voltage drops:
Again, a low ESR capacitor will result in a higher
performance output.
Paralleling Devices
Any number of ICL7660S voltage converters may be
paralleled to reduce output resistance. The reservoir
capacitor, C
2
, serves all devices while each device requires
its own pump capacitor, C
1
. The resultant output resistance
would be approximately:
Cascading Devices
The ICL7660S may be cascaded as shown to produce larger
negative multiplication of the initial supply voltage. However,
due to the finite efficiency of each device, the practical limit is
10 devices for light loads. The output voltage is defined by:
V
OUT
= -n(V
IN
),
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be
approximately the weighted sum of the individual ICL7660S
R
OUT
values.
Changing the ICL7660S Oscillator Frequency
It may be desirable in some applications, due to noise or other
considerations, to alter the oscillator frequency. This can be
achieved simply by one of several methods described below.
By connecting the Boost Pin (Pin 1) to V+, the oscillator
charge and discharge current is increased and, hence, the
oscillator frequency is increased by approximately 3
1
/
2
times. The result is a decrease in the output impedance and
ripple. This is of major importance for surface mount
applications where capacitor size and cost are critical.
Smaller capacitors, e.g. 0.1
μ
F, can be used in conjunction
with the Boost Pin in order to achieve similar output currents
compared to the device free running with C
1
= C
2
= 10
μ
F or
100
μ
F. (Refer to graph of Output Source Resistance as a
Function of Oscillator Frequency).
Increasing the oscillator frequency can also be achieved by
overdriving the oscillator from an external clock, as shown in
Figure 18. In order to prevent device latchup, a 1k
resistor
must be used in series with the clock output. In a situation
where the designer has generated the external clock
frequency using TTL logic, the addition of a 10k
pullup
resistor to V+ supply is required. Note that the pump
frequency with external clocking, as with internal clocking,
will be
1
/
2
of the clock frequency. Output transitions occur on
the positive going edge of the clock.
It is also possible to increase the conversion efficiency of the
ICL7660S at low load levels by lowering the oscillator
frequency. This reduces the switching losses, and is shown
in Figure 19. However, lowering the oscillator frequency will
cause an undesirable increase in the impedance of the
pump (C
1
) and reservoir (C
2
) capacitors; this is overcome by
increasing the values of C
1
and C
2
by the same factor that
the frequency has been reduced. For example, the addition
of a 100pF capacitor between pin 7 (OSC and V+ will lower
the oscillator frequency to 1kHz from its nominal frequency
of 10kHz (a multiple of 10), and thereby necessitate
corresponding increase in the value of C
1
and C
2
(from
10
μ
F to 100
μ
F).
R
O
2 x 23 +
+ 4 x ESR
C1
+
ESR
C2
R
O
46 + 20 + 5 x ESR
C
R
OUT
=
R
OUT
(of ICL7660S)
n (number of devices)
V
RIPPLE
C2
×
-------------------------------------------
2 ESRC2
IOUT
×
+
1
2
3
4
8
7
6
5
+
-
10
μ
F
ICL7660S
V
OUT
V+
+
-
10
μ
F
V+
CMOS
GATE
1k
FIGURE 15. EXTERNAL CLOCKING
ICL7660S
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